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This allows unit tests to control whether sgt's are viewed as IOMMU'able or not. JIRA NVGPU-1443 Change-Id: Ib0d17993fe05ecc9130c1d5bfd528795a5359ce5 Signed-off-by: Philip Elcan <pelcan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1962782 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
65 lines
1.9 KiB
C
65 lines
1.9 KiB
C
/*
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* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef __NVGPU_OS_POSIX_H__
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#define __NVGPU_OS_POSIX_H__
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#include <nvgpu/gk20a.h>
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struct nvgpu_posix_io_callbacks;
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struct nvgpu_os_posix {
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struct gk20a g;
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/*
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* IO callbacks for handling the nvgpu IO accessors.
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*/
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struct nvgpu_posix_io_callbacks *callbacks;
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/*
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* Memory-mapped register space for unit tests.
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*/
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struct nvgpu_list_node reg_space_head;
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int error_code;
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/*
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* List to record sequence of register writes.
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*/
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struct nvgpu_list_node recorder_head;
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bool recording;
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/*
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* Parameters to change the behavior of MM-related functions
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*/
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bool mm_is_iommuable;
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bool mm_sgt_is_iommuable;
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};
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static inline struct nvgpu_os_posix *nvgpu_os_posix_from_gk20a(struct gk20a *g)
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{
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return container_of(g, struct nvgpu_os_posix, g);
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}
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#endif
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