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aa05648fd6
-implement mm ops init_mm_setup_hw This will also call *fault*setup* that will do s/w and h/w set up required to get mmu fault info -implement s/w set up for copying mmu faults Two shadow fault buffers are pre allocated which will be used to copy fault info. One for copying from fault snap registers/nonreplayable h/w fault buffers and one for replay h/w fault buffers -implement s/w set up for buffering mmu faults Replayable/Non-replayable fault buffers are mapped in BAR2 virtual/physical address space. These buffers are circular buffers in terms of address calculation. Currently there are num host channels buffers -configure h/w for buffering mmu faults if s/w set up is successful, configure h/w registers to enable buffered mode of mmu faults -if both s/w and h/w set up are successful, enable corresponding hub interrupts -implement new ops, fault_info_buf_deinit This will be called during gk20a_mm_destroy to disable hub intr and de-allocate shadow fault buf that is used to copy mmu fault info during mmu fault handling -implement mm ops remove_bar2_vm This will also unmap and free fault buffers mapped in BAR2 if fault buffers were allocated JIRA GPUT19X-7 JIRA GPUT19X-12 Change-Id: I53a38eddbb0a50a1f2024600583f2aae1f1fba6d Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master/r/1492682 Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> GVS: Gerrit_Virtual_Submit
71 lines
2.0 KiB
C
71 lines
2.0 KiB
C
/*
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* GV11B master
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*
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* Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#include <linux/types.h>
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#include "gk20a/gk20a.h"
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#include "gp10b/mc_gp10b.h"
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#include "mc_gv11b.h"
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#include "fb_gv11b.h"
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#include <nvgpu/hw/gv11b/hw_mc_gv11b.h>
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static void mc_gv11b_intr_enable(struct gk20a *g)
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{
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u32 eng_intr_mask = gk20a_fifo_engine_interrupt_mask(g);
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gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_STALLING),
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0xffffffff);
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gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_NONSTALLING),
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0xffffffff);
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gv11b_fb_disable_hub_intr(g, STALL_REG_INDEX, HUB_INTR_TYPE_ALL);
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g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_STALLING] =
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mc_intr_pfifo_pending_f() |
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mc_intr_hub_pending_f() |
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mc_intr_priv_ring_pending_f() |
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mc_intr_pbus_pending_f() |
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mc_intr_ltc_pending_f() |
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eng_intr_mask;
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g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_NONSTALLING] =
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mc_intr_pfifo_pending_f()
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| eng_intr_mask;
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/* TODO: Enable PRI faults for HUB ECC err intr */
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gv11b_fb_enable_hub_intr(g, STALL_REG_INDEX, g->mm.hub_intr_types);
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gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_STALLING),
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g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_STALLING]);
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gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_NONSTALLING),
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g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_NONSTALLING]);
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}
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static bool gv11b_mc_is_intr_hub_pending(struct gk20a *g, u32 mc_intr_0)
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{
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return ((mc_intr_0 & mc_intr_hub_pending_f()) ? true : false);
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}
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void gv11b_init_mc(struct gpu_ops *gops)
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{
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gp10b_init_mc(gops);
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gops->mc.intr_enable = mc_gv11b_intr_enable;
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gops->mc.is_intr_hub_pending = gv11b_mc_is_intr_hub_pending;
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}
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