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6277d57936
Add new ioctl api for setting longer timeslice and get timeslice inside 'dbg' dev node. Update ioctl gpu_get_characteristic to pass the max timeslice value Add debugfs to access and change the max timeslice value Bug 1842244 Change-Id: I7e80f59162cf5d90496f9752fc128f5fa8dcc7d2 Signed-off-by: Mayur Poojary <mpoojary@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2471569 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com> Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
43 lines
1.7 KiB
C
43 lines
1.7 KiB
C
/*
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* Copyright (c) 2017-2021, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_DBG_VGPU_H
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#define NVGPU_DBG_VGPU_H
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struct dbg_session_gk20a;
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struct nvgpu_dbg_reg_op;
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struct nvgpu_profiler_object;
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struct gk20a;
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struct nvgpu_channel;
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int vgpu_exec_regops(struct gk20a *g,
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struct nvgpu_tsg *tsg,
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struct nvgpu_profiler_object *prof,
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struct nvgpu_dbg_reg_op *ops,
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u32 num_ops,
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u32 *flags);
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int vgpu_dbg_set_powergate(struct dbg_session_gk20a *dbg_s,
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bool disable_powergate);
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int vgpu_tsg_set_long_timeslice(struct nvgpu_tsg *tsg, u32 timeslice_us);
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#endif /* NVGPU_DBG_VGPU_H */
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