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Creates sysfs nodes to read clk freq on GV100 Following sysfs nodes are created: gpcclk,xbarclk,sysclk Uses default clock source and counters for measurement Bug 200446261 Change-Id: I6903ba77fbe34e3f486f4b663e70eab4e7c5d662 Signed-off-by: absalam <absalam@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1828030 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
64 lines
2.3 KiB
C
64 lines
2.3 KiB
C
/*
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* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef CLK_GV100_H
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#define CLK_GV100_H
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#include <nvgpu/lock.h>
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#include "gk20a/gk20a.h"
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#define CLK_NAMEMAP_INDEX_GPCCLK 0x00
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#define CLK_NAMEMAP_INDEX_XBARCLK 0x02
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#define CLK_NAMEMAP_INDEX_SYSCLK 0x07 /* SYSPLL */
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#define CLK_NAMEMAP_INDEX_DRAMCLK 0x20 /* DRAMPLL */
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#define CLK_DEFAULT_CNTRL_SETTLE_RETRIES 10
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#define CLK_DEFAULT_CNTRL_SETTLE_USECS 5
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#define CLK_MAX_CNTRL_REGISTERS 2
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#define XTAL_CNTR_CLKS 27000 /* 1000usec at 27KHz XTAL */
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#define XTAL_CNTR_DELAY 10000 /* we need acuracy up to the 10ms */
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#define XTAL_SCALE_TO_KHZ 1
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#define NUM_NAMEMAPS (3U)
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#define XTAL4X_KHZ 108000
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u32 gv100_get_rate_cntr(struct gk20a *g, struct namemap_cfg *c);
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struct namemap_cfg {
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u32 namemap;
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u32 is_enable; /* Namemap enabled */
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u32 is_counter; /* Using cntr */
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struct gk20a *g;
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struct {
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u32 reg_ctrl_addr;
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u32 reg_ctrl_idx;
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u32 reg_cntr_addr[CLK_MAX_CNTRL_REGISTERS];
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} cntr;
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u32 scale;
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char name[24];
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};
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int gv100_init_clk_support(struct gk20a *g);
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u32 gv100_crystal_clk_hz(struct gk20a *g);
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unsigned long gv100_clk_measure_freq(struct gk20a *g, u32 api_domain);
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int gv100_suspend_clk_support(struct gk20a *g);
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#endif /* CLK_GV100_H */
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