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2805f03aa0
MISRA rule 21.2 doesn't allow the use of macro names which start with an underscore. These leading underscores are to be removed from the macro names. This patch will fix such violations in pmgr by renaming them to follow the convention, 'NVGPU_PARENT-DIR_HEADER-NAME' when there is no keyword repetition between file name and directory or 'NVGPU_HEADER-NAME' when there is repetition. JIRA NVGPU-1028 Change-Id: I1beda400163bfc6278763161520f918fb4a3d096 Signed-off-by: smadhavan <smadhavan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1815663 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
61 lines
2.0 KiB
C
61 lines
2.0 KiB
C
/*
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* general power device structures & definitions
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*
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* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_PMGR_PWRDEV_H
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#define NVGPU_PMGR_PWRDEV_H
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#include "boardobj/boardobj.h"
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#include <nvgpu/pmuif/nvgpu_gpmu_cmdif.h>
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#include "ctrl/ctrlpmgr.h"
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#define PWRDEV_I2CDEV_DEVICE_INDEX_NONE (0xFF)
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#define PWR_DEVICE_PROV_NUM_DEFAULT 1
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struct pwr_device {
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struct boardobj super;
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u8 power_rail;
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u8 i2c_dev_idx;
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bool bIs_inforom_config;
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u32 power_corr_factor;
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};
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struct pwr_devices {
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struct boardobjgrp_e32 super;
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};
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struct pwr_device_ina3221 {
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struct pwr_device super;
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struct ctrl_pmgr_pwr_device_info_rshunt
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r_shuntm_ohm[NV_PMU_PMGR_PWR_DEVICE_INA3221_CH_NUM];
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u16 configuration;
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u16 mask_enable;
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u8 gpio_function;
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u16 curr_correct_m;
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s16 curr_correct_b;
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} ;
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int pmgr_device_sw_setup(struct gk20a *g);
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#endif /* NVGPU_PMGR_PWRDEV_H */
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