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d77785800b
MISRA Rule 10.4 only allows the usage of arithmetic operations on operands of the same essential type category. Adding "U" at the end of the integer literals to have same type of operands when an arithmetic operation is performed. This fixes violation where an arithmetic operation is performed on signed and unsigned int types. JIRA NVGPU-992 Change-Id: Ic9a911beb6d161df950ca85eb4813547603a8743 Signed-off-by: Sai Nikhil <snikhil@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1809751 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Adeel Raza <araza@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
91 lines
3.1 KiB
C
91 lines
3.1 KiB
C
/*
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* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_VOLT_RAIL_H
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#define NVGPU_VOLT_RAIL_H
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#include "boardobj/boardobj.h"
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#include "boardobj/boardobjgrp.h"
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#define CTRL_VOLT_RAIL_VOLT_DELTA_MAX_ENTRIES 0x04U
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#define CTRL_PMGR_PWR_EQUATION_INDEX_INVALID 0xFFU
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#define VOLT_GET_VOLT_RAIL(pvolt, rail_idx) \
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((struct voltage_rail *)BOARDOBJGRP_OBJ_GET_BY_IDX( \
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&((pvolt)->volt_rail_metadata.volt_rails.super), (rail_idx)))
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#define VOLT_RAIL_INDEX_IS_VALID(pvolt, rail_idx) \
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(boardobjgrp_idxisvalid( \
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&((pvolt)->volt_rail_metadata.volt_rails.super), (rail_idx)))
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#define VOLT_RAIL_VOLT_3X_SUPPORTED(pvolt) \
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(!BOARDOBJGRP_IS_EMPTY(&((pvolt)->volt_rail_metadata.volt_rails.super)))
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/*!
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* extends boardobj providing attributes common to all voltage_rails.
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*/
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struct voltage_rail {
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struct boardobj super;
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u32 boot_voltage_uv;
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u8 rel_limit_vfe_equ_idx;
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u8 alt_rel_limit_vfe_equ_idx;
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u8 ov_limit_vfe_equ_idx;
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u8 pwr_equ_idx;
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u8 volt_scale_exp_pwr_equ_idx;
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u8 volt_dev_idx_default;
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u8 volt_dev_idx_ipc_vmin;
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u8 boot_volt_vfe_equ_idx;
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u8 vmin_limit_vfe_equ_idx;
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u8 volt_margin_limit_vfe_equ_idx;
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u32 volt_margin_limit_vfe_equ_mon_handle;
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u32 rel_limit_vfe_equ_mon_handle;
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u32 alt_rel_limit_vfe_equ_mon_handle;
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u32 ov_limit_vfe_equ_mon_handle;
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struct boardobjgrpmask_e32 volt_dev_mask;
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s32 volt_delta_uv[CTRL_VOLT_RAIL_VOLT_DELTA_MAX_ENTRIES];
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};
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/*!
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* metadata of voltage rail functionality.
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*/
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struct voltage_rail_metadata {
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u8 volt_domain_hal;
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u8 pct_delta;
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u32 ext_rel_delta_uv[CTRL_VOLT_RAIL_VOLT_DELTA_MAX_ENTRIES];
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u8 logic_rail_idx;
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u8 sram_rail_idx;
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struct boardobjgrp_e32 volt_rails;
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};
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u8 volt_rail_vbios_volt_domain_convert_to_internal
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(struct gk20a *g, u8 vbios_volt_domain);
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u32 volt_rail_volt_dev_register(struct gk20a *g, struct voltage_rail
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*pvolt_rail, u8 volt_dev_idx, u8 operation_type);
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u8 volt_rail_volt_domain_convert_to_idx(struct gk20a *g, u8 volt_domain);
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int volt_rail_sw_setup(struct gk20a *g);
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int volt_rail_pmu_setup(struct gk20a *g);
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#endif /* NVGPU_VOLT_RAIL_H */
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