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7f6c782ba0
MISRA Rule 10.4 only allows the usage of arithmetic operations on operands of the same essential type category. Adding "U" at the end of the integer literals to have same type of operands when an arithmetic operation is performed. This fixes violation where an arithmetic operation is performed on signed and unsigned int types. JIRA NVGPU-992 Change-Id: Ic8e5ae1ab71c6ecdfed83deeb4f354a1d1dbe8ed Signed-off-by: Sai Nikhil <snikhil@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1810614 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Scott Long <scottl@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
85 lines
3.0 KiB
C
85 lines
3.0 KiB
C
/*
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* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_CLK_FREQ_CONTROLLER_H
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#define NVGPU_CLK_FREQ_CONTROLLER_H
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#define CTRL_CLK_CLK_FREQ_CONTROLLER_ID_ALL 0xFFU
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#define CTRL_CLK_CLK_FREQ_CONTROLLER_ID_SYS 0x00U
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#define CTRL_CLK_CLK_FREQ_CONTROLLER_ID_LTC 0x01U
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#define CTRL_CLK_CLK_FREQ_CONTROLLER_ID_XBAR 0x02U
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#define CTRL_CLK_CLK_FREQ_CONTROLLER_ID_GPC0 0x03U
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#define CTRL_CLK_CLK_FREQ_CONTROLLER_ID_GPC1 0x04U
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#define CTRL_CLK_CLK_FREQ_CONTROLLER_ID_GPC2 0x05U
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#define CTRL_CLK_CLK_FREQ_CONTROLLER_ID_GPC3 0x06U
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#define CTRL_CLK_CLK_FREQ_CONTROLLER_ID_GPC4 0x07U
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#define CTRL_CLK_CLK_FREQ_CONTROLLER_ID_GPC5 0x08U
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#define CTRL_CLK_CLK_FREQ_CONTROLLER_ID_GPCS 0x09U
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#define CTRL_CLK_CLK_FREQ_CONTROLLER_MASK_UNICAST_GPC \
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(BIT32(CTRL_CLK_CLK_FREQ_CONTROLLER_ID_GPC0) | \
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BIT32(CTRL_CLK_CLK_FREQ_CONTROLLER_ID_GPC1) | \
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BIT32(CTRL_CLK_CLK_FREQ_CONTROLLER_ID_GPC2) | \
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BIT32(CTRL_CLK_CLK_FREQ_CONTROLLER_ID_GPC3) | \
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BIT32(CTRL_CLK_CLK_FREQ_CONTROLLER_ID_GPC4) | \
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BIT32(CTRL_CLK_CLK_FREQ_CONTROLLER_ID_GPC5))
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#define CTRL_CLK_CLK_FREQ_CONTROLLER_TYPE_DISABLED 0x00U
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#define CTRL_CLK_CLK_FREQ_CONTROLLER_TYPE_PI 0x01U
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struct clk_freq_controller {
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struct boardobj super;
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u8 controller_id;
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u8 parts_freq_mode;
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bool bdisable;
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u32 clk_domain;
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s16 freq_cap_noise_unaware_vmin_above;
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s16 freq_cap_noise_unaware_vmin_below;
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s16 freq_hyst_pos_mhz;
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s16 freq_hyst_neg_mhz;
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};
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struct clk_freq_controller_pi {
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struct clk_freq_controller super;
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s32 prop_gain;
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s32 integ_gain;
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s32 integ_decay;
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s32 volt_delta_min;
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s32 volt_delta_max;
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u8 slowdown_pct_min;
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bool bpoison;
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};
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struct clk_freq_controllers {
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struct boardobjgrp_e32 super;
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u32 sampling_period_ms;
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struct boardobjgrpmask_e32 freq_ctrl_load_mask;
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u8 volt_policy_idx;
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void *pprereq_load;
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};
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int clk_freq_controller_sw_setup(struct gk20a *g);
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int clk_freq_controller_pmu_setup(struct gk20a *g);
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#endif /* NVGPU_CLK_FREQ_CONTROLLER_H */
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