mirror of
git://nv-tegra.nvidia.com/linux-nvgpu.git
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67a41e46a2
We were not using the engine_type field in device info, and the code did not handle chained entries properly. The code assumed that first entry is for graphics and second for CE, which is not always true. Improve the code to go through all entries of device_info, and preserve values across entries until we reach the last entry. Only last entry triggers a write to fifo engine info. There can also be multiple engines with same type, so accumulate interrupts and reset ids from all of them. As the code got fixed, now it reads the engine enum correctly from hardware. We used to compare that against CE0, but we should compare against CE2. gk20a_fifo_reset_engine() uses wrong constants - it is passed a internal numbering of engines, but it compares them against hardware engine enum. Change-Id: Ia59273921c602d2a090f7a5b1404afb0fca2532c Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1147746 Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
186 lines
4.7 KiB
C
186 lines
4.7 KiB
C
/*
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* Copyright (c) 2012-2016, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/*
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* Function naming determines intended use:
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*
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* <x>_r(void) : Returns the offset for register <x>.
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*
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* <x>_o(void) : Returns the offset for element <x>.
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*
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* <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
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*
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* <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
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*
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* <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
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* and masked to place it at field <y> of register <x>. This value
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* can be |'d with others to produce a full register value for
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* register <x>.
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*
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* <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
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* value can be ~'d and then &'d to clear the value of field <y> for
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* register <x>.
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*
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* <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
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* to place it at field <y> of register <x>. This value can be |'d
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* with others to produce a full register value for <x>.
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*
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* <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
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* <x> value 'r' after being shifted to place its LSB at bit 0.
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* This value is suitable for direct comparison with other unshifted
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* values appropriate for use in field <y> of register <x>.
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*
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* <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
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* field <y> of register <x>. This value is suitable for direct
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* comparison with unshifted values appropriate for use in field <y>
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* of register <x>.
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*/
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#ifndef _hw_top_gk20a_h_
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#define _hw_top_gk20a_h_
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static inline u32 top_num_gpcs_r(void)
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{
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return 0x00022430;
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}
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static inline u32 top_num_gpcs_value_v(u32 r)
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{
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return (r >> 0) & 0x1f;
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}
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static inline u32 top_tpc_per_gpc_r(void)
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{
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return 0x00022434;
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}
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static inline u32 top_tpc_per_gpc_value_v(u32 r)
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{
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return (r >> 0) & 0x1f;
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}
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static inline u32 top_num_fbps_r(void)
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{
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return 0x00022438;
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}
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static inline u32 top_num_fbps_value_v(u32 r)
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{
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return (r >> 0) & 0x1f;
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}
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static inline u32 top_device_info_r(u32 i)
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{
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return 0x00022700 + i*4;
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}
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static inline u32 top_device_info__size_1_v(void)
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{
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return 0x00000040;
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}
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static inline u32 top_device_info_chain_v(u32 r)
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{
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return (r >> 31) & 0x1;
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}
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static inline u32 top_device_info_chain_enable_v(void)
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{
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return 0x00000001;
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}
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static inline u32 top_device_info_engine_enum_v(u32 r)
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{
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return (r >> 26) & 0xf;
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}
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static inline u32 top_device_info_runlist_enum_v(u32 r)
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{
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return (r >> 21) & 0xf;
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}
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static inline u32 top_device_info_intr_enum_v(u32 r)
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{
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return (r >> 15) & 0x1f;
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}
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static inline u32 top_device_info_reset_enum_v(u32 r)
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{
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return (r >> 9) & 0x1f;
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}
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static inline u32 top_device_info_type_enum_v(u32 r)
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{
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return (r >> 2) & 0x1fffffff;
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}
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static inline u32 top_device_info_type_enum_graphics_v(void)
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{
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return 0x00000000;
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}
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static inline u32 top_device_info_type_enum_graphics_f(void)
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{
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return 0x0;
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}
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static inline u32 top_device_info_type_enum_copy2_v(void)
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{
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return 0x00000003;
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}
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static inline u32 top_device_info_type_enum_copy2_f(void)
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{
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return 0xc;
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}
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static inline u32 top_device_info_engine_v(u32 r)
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{
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return (r >> 5) & 0x1;
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}
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static inline u32 top_device_info_runlist_v(u32 r)
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{
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return (r >> 4) & 0x1;
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}
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static inline u32 top_device_info_intr_v(u32 r)
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{
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return (r >> 3) & 0x1;
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}
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static inline u32 top_device_info_reset_v(u32 r)
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{
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return (r >> 2) & 0x1;
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}
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static inline u32 top_device_info_entry_v(u32 r)
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{
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return (r >> 0) & 0x3;
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}
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static inline u32 top_device_info_entry_not_valid_v(void)
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{
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return 0x00000000;
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}
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static inline u32 top_device_info_entry_enum_v(void)
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{
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return 0x00000002;
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}
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static inline u32 top_device_info_entry_engine_type_v(void)
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{
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return 0x00000003;
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}
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static inline u32 top_fs_status_fbp_r(void)
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{
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return 0x00022548;
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}
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static inline u32 top_fs_status_fbp_cluster_v(u32 r)
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{
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return (r >> 0) & 0xffff;
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}
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static inline u32 top_fs_status_fbp_cluster_enable_v(void)
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{
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return 0x00000000;
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}
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static inline u32 top_fs_status_fbp_cluster_enable_f(void)
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{
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return 0x0;
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}
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static inline u32 top_fs_status_fbp_cluster_disable_v(void)
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{
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return 0x00000001;
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}
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static inline u32 top_fs_status_fbp_cluster_disable_f(void)
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{
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return 0x1;
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}
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#endif
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