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82c94e2291
MISRA rule 21.2 doesn't allow the use of macro names which start with an underscore. These leading underscores are to be removed from the macro names. This patch will fix such violations in gv11b by renaming them to follow the convention, 'NVGPU_PARENT-DIR_HEADER-NAME' when there is no keyword repetition between file name and directory or 'NVGPU_HEADER-NAME' when there is repetition. JIRA NVGPU-1028 Change-Id: Ibf6b54b2a0d3f4fbfacb554b78b88911341b960f Signed-off-by: smadhavan <smadhavan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1815567 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Adeel Raza <araza@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
43 lines
2.0 KiB
C
43 lines
2.0 KiB
C
/*
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*
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* Tegra GV11B GPU Driver Register Ops
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*
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* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_REGOPS_GV11B_H
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#define NVGPU_REGOPS_GV11B_H
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const struct regop_offset_range *gv11b_get_global_whitelist_ranges(void);
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u64 gv11b_get_global_whitelist_ranges_count(void);
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const struct regop_offset_range *gv11b_get_context_whitelist_ranges(void);
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u64 gv11b_get_context_whitelist_ranges_count(void);
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const u32 *gv11b_get_runcontrol_whitelist(void);
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u64 gv11b_get_runcontrol_whitelist_count(void);
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const struct regop_offset_range *gv11b_get_runcontrol_whitelist_ranges(void);
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u64 gv11b_get_runcontrol_whitelist_ranges_count(void);
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const u32 *gv11b_get_qctl_whitelist(void);
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u64 gv11b_get_qctl_whitelist_count(void);
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const struct regop_offset_range *gv11b_get_qctl_whitelist_ranges(void);
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u64 gv11b_get_qctl_whitelist_ranges_count(void);
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int gv11b_apply_smpc_war(struct dbg_session_gk20a *dbg_s);
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#endif /* NVGPU_REGOPS_GV11B_H */
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