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3e6779d554
MISRA rule 14.4 doesn't allow the usage of integer types as booleans in the controlling expression of an if statement or an iteration statement. Fix violations where the integer variables err, ret, status are used as booleans in the controlling expression of if and loop statements. JIRA NVGPU-1019 Change-Id: I36494e84ee6cd4a108e2a539f48f102e47e2f7f4 Signed-off-by: Amurthyreddy <amurthyreddy@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1926820 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
138 lines
4.2 KiB
C
138 lines
4.2 KiB
C
/*
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* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_CLK_PROG_H
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#define NVGPU_CLK_PROG_H
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#include <nvgpu/pmuif/ctrlclk.h>
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#include <nvgpu/pmuif/ctrlboardobj.h>
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#include <nvgpu/pmuif/nvgpu_gpmu_cmdif.h>
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#include <nvgpu/boardobjgrp_e32.h>
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#include <nvgpu/boardobjgrp_e255.h>
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#include <nvgpu/boardobjgrpmask.h>
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int clk_prog_sw_setup(struct gk20a *g);
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int clk_prog_pmu_setup(struct gk20a *g);
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struct clk_prog_1x_master;
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typedef int vf_flatten(struct gk20a *g, struct clk_pmupstate *pclk,
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struct clk_prog_1x_master *p1xmaster,
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u8 clk_domain_idx, u16 *pfreqmaxlastmhz);
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typedef u32 vf_lookup(struct gk20a *g, struct clk_pmupstate *pclk,
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struct clk_prog_1x_master *p1xmaster,
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u8 *slave_clk_domain_idx, u16 *pclkmhz,
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u32 *pvoltuv, u8 rail);
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typedef int get_slaveclk(struct gk20a *g, struct clk_pmupstate *pclk,
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struct clk_prog_1x_master *p1xmaster,
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u8 slave_clk_domain_idx, u16 *pclkmhz,
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u16 masterclkmhz);
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typedef int get_fpoints(struct gk20a *g, struct clk_pmupstate *pclk,
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struct clk_prog_1x_master *p1xmaster,
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u32 *pfpointscount,
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u16 **ppfreqpointsinmhz, u8 rail);
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struct clk_progs {
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struct boardobjgrp_e255 super;
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u8 slave_entry_count;
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u8 vf_entry_count;
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u8 vf_sec_entry_count;
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};
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struct clk_prog {
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struct boardobj super;
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};
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struct clk_prog_1x {
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struct clk_prog super;
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u8 source;
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u16 freq_max_mhz;
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union ctrl_clk_clk_prog_1x_source_data source_data;
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};
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struct clk_prog_1x_master {
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struct clk_prog_1x super;
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bool b_o_c_o_v_enabled;
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struct ctrl_clk_clk_prog_1x_master_vf_entry *p_vf_entries;
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struct ctrl_clk_clk_delta deltas;
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union ctrl_clk_clk_prog_1x_master_source_data source_data;
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vf_flatten *vfflatten;
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vf_lookup *vflookup;
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get_fpoints *getfpoints;
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get_slaveclk *getslaveclk;
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};
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struct clk_prog_1x_master_ratio {
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struct clk_prog_1x_master super;
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struct ctrl_clk_clk_prog_1x_master_ratio_slave_entry *p_slave_entries;
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};
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struct clk_prog_1x_master_table {
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struct clk_prog_1x_master super;
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struct ctrl_clk_clk_prog_1x_master_table_slave_entry *p_slave_entries;
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};
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struct clk_prog_3x_master {
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bool b_o_c_o_v_enabled;
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struct ctrl_clk_clk_prog_1x_master_vf_entry *p_vf_entries;
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struct ctrl_clk_clk_delta deltas;
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union ctrl_clk_clk_prog_1x_master_source_data source_data;
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vf_flatten *vfflatten;
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vf_lookup *vflookup;
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get_fpoints *getfpoints;
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get_slaveclk *getslaveclk;
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};
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struct clk_prog_3x_master_ratio {
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struct ctrl_clk_clk_prog_1x_master_ratio_slave_entry *p_slave_entries;
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};
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struct clk_prog_3x_master_table {
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struct ctrl_clk_clk_prog_1x_master_table_slave_entry *p_slave_entries;
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};
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struct clk_prog_35_master {
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struct clk_prog_1x super;
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struct clk_prog_3x_master master;
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struct ctrl_clk_clk_prog_35_master_sec_vf_entry_voltrail
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*p_voltrail_sec_vf_entries;
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};
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struct clk_prog_35_master_ratio {
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struct clk_prog_35_master super;
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struct clk_prog_3x_master_ratio ratio;
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};
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struct clk_prog_35_master_table {
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struct clk_prog_35_master super;
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struct clk_prog_3x_master_table table;
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};
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#define CLK_CLK_PROG_GET(pclk, idx) \
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((struct clk_prog *)BOARDOBJGRP_OBJ_GET_BY_IDX( \
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&pclk->clk_progobjs.super.super, (u8)(idx)))
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#endif /* NVGPU_CLK_PROG_H */
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