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ae6e4d0572
For a given channel, userd_iova is computed as an offset from fifo->userd address. If nvlink is enabled we need fifo->userd buffer to be physically contiguous, as nvlink bypasses IOMMU. Otherwise, it may result in loading PBDMA from an invalid location in memory. This manifests most of the time with either channel timeout (GP_PUT loaded with 0, hence no progress) or GPPTR Invalid Error (GP_PUT loaded with out of range index). Use NVGPU_DMA_FORCE_CONTIGUOUS for fifo->userd buffer, when nvlink is enabled. Bug 2422486 Change-Id: I99d585ee196534025522a1cbd74fb4e4c03df98e Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1954802 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Deepak Nibade <dnibade@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>