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cd4b2f642c
Refactor read accesses to the ccsr_channel register for channel state to be done via a channel HAL op for all chips. A new op called read_state is added for this; information needed by other units is collected in a new struct nvgpu_channel_hw_state. Jira NVGPU-1307 Change-Id: Iff9385c08e17ac086d97f5771a54b56b2727e3c4 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2017266 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
37 lines
1.6 KiB
C
37 lines
1.6 KiB
C
/*
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* Copyright (c) 2011-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef FIFO_CHANNEL_GK20A_H
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#define FIFO_CHANNEL_GK20A_H
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struct channel_gk20a;
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struct gk20a;
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struct nvgpu_channel_hw_state;
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void gk20a_channel_enable(struct channel_gk20a *ch);
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void gk20a_channel_disable(struct channel_gk20a *ch);
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void gk20a_channel_unbind(struct channel_gk20a *ch);
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void gk20a_channel_read_state(struct gk20a *g, struct channel_gk20a *ch,
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struct nvgpu_channel_hw_state *state);
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#endif /* FIFO_CHANNEL_GK20A_H */
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