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44e4d69734
Isolate the write to ccsr_channel_force_ctx_reload behind a HAL op. Jira NVGPU-1307 Change-Id: Iaef7d740f4a89e4a45c7de28f001a7dea98ce066 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2017268 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
75 lines
2.5 KiB
C
75 lines
2.5 KiB
C
/*
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* Copyright (c) 2014-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/channel.h>
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#include <nvgpu/log.h>
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#include <nvgpu/atomic.h>
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#include <nvgpu/io.h>
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#include <nvgpu/barrier.h>
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#include <nvgpu/gk20a.h>
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#include "channel_gm20b.h"
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#include <nvgpu/hw/gm20b/hw_ccsr_gm20b.h>
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#include <nvgpu/hw/gm20b/hw_ram_gm20b.h>
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void gm20b_channel_bind(struct channel_gk20a *c)
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{
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struct gk20a *g = c->g;
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u32 inst_ptr = nvgpu_inst_block_addr(g, &c->inst_block)
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>> ram_in_base_shift_v();
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nvgpu_log_info(g, "bind channel %d inst ptr 0x%08x",
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c->chid, inst_ptr);
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gk20a_writel(g, ccsr_channel_inst_r(c->chid),
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ccsr_channel_inst_ptr_f(inst_ptr) |
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nvgpu_aperture_mask(g, &c->inst_block,
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ccsr_channel_inst_target_sys_mem_ncoh_f(),
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ccsr_channel_inst_target_sys_mem_coh_f(),
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ccsr_channel_inst_target_vid_mem_f()) |
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ccsr_channel_inst_bind_true_f());
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gk20a_writel(g, ccsr_channel_r(c->chid),
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(gk20a_readl(g, ccsr_channel_r(c->chid)) &
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~ccsr_channel_enable_set_f(~U32(0U))) |
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ccsr_channel_enable_set_true_f());
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nvgpu_smp_wmb();
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nvgpu_atomic_set(&c->bound, true);
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}
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u32 gm20b_channel_count(struct gk20a *g)
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{
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return ccsr_channel__size_1_v();
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}
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void gm20b_channel_force_ctx_reload(struct channel_gk20a *ch)
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{
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struct gk20a *g = ch->g;
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u32 reg = gk20a_readl(g, ccsr_channel_r(ch->chid));
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gk20a_writel(g, ccsr_channel_r(ch->chid),
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reg | ccsr_channel_force_ctx_reload_true_f());
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}
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