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9767366c60
A new unit pbdma_status is added. The unit provides a HAL ops function pointer read_pbdma_status_info() to read and produce a struct of type nvgpu_pbdma_status_info. Additionally, the unit provides public APIs to retrieve data from the struct nvgpu_pbdma_status_info. Jira NVGPU-1311 Change-Id: Ic89c78703c3738b91be8d18ba970a591658d4022 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2019976 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
154 lines
5.4 KiB
C
154 lines
5.4 KiB
C
/*
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* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/io.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/pbdma_status.h>
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#include <nvgpu/hw/gm20b/hw_fifo_gm20b.h>
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#include "pbdma_status_gm20b.h"
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static void populate_invalid_chsw_status_info(
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struct nvgpu_pbdma_status_info *status_info)
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{
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status_info->id = PBDMA_STATUS_ID_INVALID;
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status_info->id_type = PBDMA_STATUS_ID_TYPE_INVALID;
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status_info->next_id = PBDMA_STATUS_NEXT_ID_INVALID;
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status_info->next_id_type = PBDMA_STATUS_NEXT_ID_TYPE_INVALID;
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status_info->chsw_status = NVGPU_PBDMA_CHSW_STATUS_INVALID;
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}
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static void populate_valid_chsw_status_info(
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struct nvgpu_pbdma_status_info *status_info)
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{
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bool id_type_tsg;
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u32 engine_status = status_info->pbdma_reg_status;
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status_info->id =
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fifo_pbdma_status_id_v(status_info->pbdma_reg_status);
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id_type_tsg = fifo_pbdma_status_id_type_v(engine_status) ==
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fifo_pbdma_status_id_type_tsgid_v();
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status_info->id_type =
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id_type_tsg ? PBDMA_STATUS_ID_TYPE_TSGID :
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PBDMA_STATUS_ID_TYPE_CHID;
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status_info->next_id = PBDMA_STATUS_NEXT_ID_INVALID;
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status_info->next_id_type = PBDMA_STATUS_NEXT_ID_TYPE_INVALID;
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status_info->chsw_status = NVGPU_PBDMA_CHSW_STATUS_VALID;
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}
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static void populate_load_chsw_status_info(
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struct nvgpu_pbdma_status_info *status_info)
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{
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bool next_id_type_tsg;
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u32 engine_status = status_info->pbdma_reg_status;
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status_info->id = PBDMA_STATUS_ID_INVALID;
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status_info->id_type = PBDMA_STATUS_ID_TYPE_INVALID;
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status_info->next_id =
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fifo_pbdma_status_next_id_type_v(
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status_info->pbdma_reg_status);
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next_id_type_tsg = fifo_pbdma_status_next_id_type_v(engine_status) ==
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fifo_pbdma_status_next_id_type_tsgid_v();
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status_info->next_id_type =
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next_id_type_tsg ? PBDMA_STATUS_NEXT_ID_TYPE_TSGID :
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PBDMA_STATUS_NEXT_ID_TYPE_CHID;
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status_info->chsw_status = NVGPU_PBDMA_CHSW_STATUS_LOAD;
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}
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static void populate_save_chsw_status_info(
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struct nvgpu_pbdma_status_info *status_info)
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{
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bool id_type_tsg;
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u32 engine_status = status_info->pbdma_reg_status;
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status_info->id =
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fifo_pbdma_status_id_v(status_info->pbdma_reg_status);
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id_type_tsg = fifo_pbdma_status_id_type_v(engine_status) ==
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fifo_pbdma_status_id_type_tsgid_v();
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status_info->id_type =
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id_type_tsg ? PBDMA_STATUS_ID_TYPE_TSGID :
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PBDMA_STATUS_ID_TYPE_CHID;
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status_info->next_id = PBDMA_STATUS_NEXT_ID_INVALID;
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status_info->next_id_type = PBDMA_STATUS_NEXT_ID_TYPE_INVALID;
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status_info->chsw_status = NVGPU_PBDMA_CHSW_STATUS_SAVE;
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}
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static void populate_switch_chsw_status_info(
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struct nvgpu_pbdma_status_info *status_info)
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{
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bool id_type_tsg;
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bool next_id_type_tsg;
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u32 engine_status = status_info->pbdma_reg_status;
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status_info->id =
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fifo_pbdma_status_id_v(status_info->pbdma_reg_status);
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id_type_tsg = fifo_pbdma_status_id_type_v(engine_status) ==
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fifo_pbdma_status_id_type_tsgid_v();
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status_info->id_type =
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id_type_tsg ? PBDMA_STATUS_ID_TYPE_TSGID :
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PBDMA_STATUS_ID_TYPE_CHID;
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status_info->next_id =
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fifo_pbdma_status_next_id_type_v(
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status_info->pbdma_reg_status);
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next_id_type_tsg = fifo_pbdma_status_next_id_type_v(engine_status) ==
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fifo_pbdma_status_next_id_type_tsgid_v();
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status_info->next_id_type =
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next_id_type_tsg ? PBDMA_STATUS_NEXT_ID_TYPE_TSGID :
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PBDMA_STATUS_NEXT_ID_TYPE_CHID;
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status_info->chsw_status = NVGPU_PBDMA_CHSW_STATUS_SWITCH;
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}
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void gm20b_read_pbdma_status_info(struct gk20a *g, u32 pbdma_id,
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struct nvgpu_pbdma_status_info *status)
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{
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u32 pbdma_reg_status;
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u32 pbdma_channel_status;
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(void) memset(status, 0, sizeof(*status));
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pbdma_reg_status = nvgpu_readl(g, fifo_pbdma_status_r(pbdma_id));
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status->pbdma_reg_status = pbdma_reg_status;
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/* populate the chsw related info */
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pbdma_channel_status = fifo_pbdma_status_chan_status_v(
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pbdma_reg_status);
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status->pbdma_channel_status = pbdma_channel_status;
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if (pbdma_channel_status == fifo_pbdma_status_chan_status_valid_v()) {
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populate_valid_chsw_status_info(status);
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} else if (pbdma_channel_status ==
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fifo_pbdma_status_chan_status_chsw_load_v()) {
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populate_load_chsw_status_info(status);
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} else if (pbdma_channel_status ==
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fifo_pbdma_status_chan_status_chsw_save_v()) {
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populate_save_chsw_status_info(status);
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} else if (pbdma_channel_status ==
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fifo_pbdma_status_chan_status_chsw_switch_v()) {
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populate_switch_chsw_status_info(status);
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} else {
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populate_invalid_chsw_status_info(status);
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}
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}
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