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061aa66adc
The following changes are done in this patch. 1) gk20a_fifo_get_engine_info() is moved to common/fifo/engine.c and is renamed to gk20a_fifo_get_active_engine_info() to reflect accurately the purpose of the function. 2) move the definition of enum fifo_engine to <nvgpu/engines.h> and add the prefix NVGPU_ 3) move the following functions related to engines in fifo_gk20a.c to common/fifo/engines.c and replace their signature by adding the prefix nvgpu_engine and removing gk20a_fifo. gk20a_fifo_get_active_engine_info gk20a_fifo_engine_enum_from_type gk20a_fifo_get_engine_ids gk20a_fifo_is_valid_engine_id gk20a_fifo_get_gr_engine_id gk20a_fifo_act_eng_interrupt_mask gk20a_fifo_engine_interrupt_mask gk20a_fifo_get_all_ce_engine_reset_mask Jira NVGPU-1315 Change-Id: I63d9dcd905a0bebcc9a4c65776cf6ec7a0837acf Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2011298 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
126 lines
3.7 KiB
C
126 lines
3.7 KiB
C
/*
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* GV100 master
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*
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* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/types.h>
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#include <nvgpu/io.h>
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#include <nvgpu/mc.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/unit.h>
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#include <nvgpu/bug.h>
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#include <nvgpu/engines.h>
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#include "mc_gp10b.h"
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#include "mc_gv100.h"
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#include <nvgpu/hw/gv100/hw_mc_gv100.h>
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void mc_gv100_intr_enable(struct gk20a *g)
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{
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u32 eng_intr_mask = nvgpu_engine_interrupt_mask(g);
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gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_STALLING),
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0xffffffffU);
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gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_NONSTALLING),
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0xffffffffU);
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g->mc_intr_mask_restore[NVGPU_MC_INTR_STALLING] =
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mc_intr_pfifo_pending_f() |
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mc_intr_hub_pending_f() |
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mc_intr_priv_ring_pending_f() |
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mc_intr_pbus_pending_f() |
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mc_intr_ltc_pending_f() |
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mc_intr_nvlink_pending_f() |
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eng_intr_mask;
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g->mc_intr_mask_restore[NVGPU_MC_INTR_NONSTALLING] =
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mc_intr_pfifo_pending_f()
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| eng_intr_mask;
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gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_STALLING),
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g->mc_intr_mask_restore[NVGPU_MC_INTR_STALLING]);
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gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_NONSTALLING),
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g->mc_intr_mask_restore[NVGPU_MC_INTR_NONSTALLING]);
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}
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bool gv100_mc_is_intr_nvlink_pending(struct gk20a *g, u32 mc_intr_0)
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{
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return (((mc_intr_0 & mc_intr_nvlink_pending_f()) != 0U) ? true : false);
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}
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bool gv100_mc_is_stall_and_eng_intr_pending(struct gk20a *g, u32 act_eng_id,
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u32 *eng_intr_pending)
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{
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u32 mc_intr_0 = gk20a_readl(g, mc_intr_r(0));
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u32 stall_intr, eng_intr_mask;
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eng_intr_mask = nvgpu_engine_act_interrupt_mask(g, act_eng_id);
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*eng_intr_pending = mc_intr_0 & eng_intr_mask;
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stall_intr = mc_intr_pfifo_pending_f() |
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mc_intr_hub_pending_f() |
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mc_intr_priv_ring_pending_f() |
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mc_intr_pbus_pending_f() |
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mc_intr_ltc_pending_f() |
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mc_intr_nvlink_pending_f();
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nvgpu_log(g, gpu_dbg_info | gpu_dbg_intr,
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"mc_intr_0 = 0x%08x, eng_intr = 0x%08x",
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mc_intr_0 & stall_intr, *eng_intr_pending);
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return (mc_intr_0 & (eng_intr_mask | stall_intr)) != 0U;
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}
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u32 gv100_mc_reset_mask(struct gk20a *g, enum nvgpu_unit unit)
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{
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u32 mask = 0;
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switch(unit) {
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case NVGPU_UNIT_FIFO:
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mask = mc_enable_pfifo_enabled_f();
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break;
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case NVGPU_UNIT_PERFMON:
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mask = mc_enable_perfmon_enabled_f();
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break;
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case NVGPU_UNIT_GRAPH:
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mask = mc_enable_pgraph_enabled_f();
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break;
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case NVGPU_UNIT_BLG:
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mask = mc_enable_blg_enabled_f();
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break;
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case NVGPU_UNIT_PWR:
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mask = mc_enable_pwr_enabled_f();
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break;
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case NVGPU_UNIT_NVDEC:
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mask = mc_enable_nvdec_enabled_f();
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break;
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default:
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nvgpu_err(g, "unknown reset unit %d", unit);
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BUG();
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break;
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}
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return mask;
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}
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