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492b3e05fe
As a part of regoranizing clk_arb code, This patch does the folowing 1. Move clk_arb HAL files under common/clk_arb unit. 2. Move clk_arb from common/pmu to common/clk_arb. 3. Append public functions with nvgpu. 4. Make local functions as static. Jira NVGPU-1966 Change-Id: If45c3dbfc4bbe74fe8d30e33e64894d553f3cda5 Signed-off-by: Abdul Salam <absalam@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2027335 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
112 lines
3.9 KiB
C
112 lines
3.9 KiB
C
/*
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* general clock structures & definitions
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*
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* Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_CLK_CLK_H
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#define NVGPU_CLK_CLK_H
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#include <nvgpu/types.h>
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#include "clk_vin.h"
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#include "clk_fll.h"
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#include "clk_domain.h"
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#include "clk_prog.h"
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#include "clk_mclk.h"
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#include "clk_freq_controller.h"
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#include "clk_freq_domain.h"
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#define NV_PERF_DOMAIN_4X_CLOCK_DOMAIN_SKIP 0x10U
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#define NV_PERF_DOMAIN_4X_CLOCK_DOMAIN_MASK 0x1FU
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#define NV_PERF_DOMAIN_4X_CLOCK_DOMAIN_SHIFT 0U
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#define BOOT_GPCCLK_MHZ 952U
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struct gk20a;
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int clk_set_boot_fll_clk(struct gk20a *g);
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struct clockentry {
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u8 vbios_clk_domain;
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u8 clk_which;
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u8 perf_index;
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u32 api_clk_domain;
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};
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struct change_fll_clk {
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u32 api_clk_domain;
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u16 clkmhz;
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u32 voltuv;
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};
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#define NV_PERF_HEADER_4X_CLOCKS_DOMAINS_MAX_NUMCLKS 9U
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struct vbios_clock_domain {
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u8 clock_type;
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u8 num_domains;
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struct clockentry clock_entry[NV_PERF_HEADER_4X_CLOCKS_DOMAINS_MAX_NUMCLKS];
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};
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struct vbios_clocks_table_1x_hal_clock_entry {
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u32 domain;
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bool b_noise_aware_capable;
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u8 clk_vf_curve_count;
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};
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#define NV_PERF_HEADER_4X_CLOCKS_DOMAINS_4_GPC2CLK 0U
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#define NV_PERF_HEADER_4X_CLOCKS_DOMAINS_4_XBAR2CLK 1U
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#define NV_PERF_HEADER_4X_CLOCKS_DOMAINS_4_DRAMCLK 2U
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#define NV_PERF_HEADER_4X_CLOCKS_DOMAINS_4_SYS2CLK 3U
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#define NV_PERF_HEADER_4X_CLOCKS_DOMAINS_4_HUB2CLK 4U
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#define NV_PERF_HEADER_4X_CLOCKS_DOMAINS_4_MSDCLK 5U
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#define NV_PERF_HEADER_4X_CLOCKS_DOMAINS_4_PWRCLK 6U
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#define NV_PERF_HEADER_4X_CLOCKS_DOMAINS_4_DISPCLK 7U
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#define NV_PERF_HEADER_4X_CLOCKS_DOMAINS_4_NUMCLKS 8U
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#define PERF_CLK_MCLK 0U
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#define PERF_CLK_DISPCLK 1U
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#define PERF_CLK_GPC2CLK 2U
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#define PERF_CLK_HOSTCLK 3U
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#define PERF_CLK_LTC2CLK 4U
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#define PERF_CLK_SYS2CLK 5U
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#define PERF_CLK_HUB2CLK 6U
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#define PERF_CLK_LEGCLK 7U
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#define PERF_CLK_MSDCLK 8U
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#define PERF_CLK_XCLK 9U
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#define PERF_CLK_PWRCLK 10U
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#define PERF_CLK_XBAR2CLK 11U
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#define PERF_CLK_PCIEGENCLK 12U
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#define PERF_CLK_NUM 13U
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struct nvgpu_set_fll_clk;
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int clk_domain_print_vf_table(struct gk20a *g, u32 clkapidomain);
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int clk_domain_get_f_or_v(struct gk20a *g, u32 clkapidomain,
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u16 *pclkmhz, u32 *pvoltuv, u8 railidx);
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int clk_domain_freq_to_volt(struct gk20a *g, u8 clkdomain_idx,
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u32 *pclkmhz, u32 *pvoltuv, u8 railidx);
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int clk_domain_volt_to_freq( struct gk20a *g, u8 clkdomain_idx,
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u32 *pclkmhz, u32 *pvoltuv, u8 railidx);
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int clk_set_fll_clks(struct gk20a *g, struct nvgpu_set_fll_clk *setfllclk);
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int clk_pmu_freq_controller_load(struct gk20a *g, bool bload, u8 bit_idx);
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int clk_pmu_freq_effective_avg_load(struct gk20a *g, bool bload);
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int clk_freq_effective_avg(struct gk20a *g, u32 *freqkHz, u32 clkDomainMask);
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#endif /* NVGPU_CLK_CLK_H */
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