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20b15e6f40
sema cmdbuf specific functions are only for the sync functionality of nvgpu and do not belong to fifo. construct files sema_cmdbuf_gk20a.h and sema_cmdbuf_gk20a.c under common/sync to contain the syncpt specific cmdbuf functions for arch gk20a. Jira NVGPU-1308 Change-Id: Iebeebe7a3de627f2de08d4ced74bb1aabf1eb53c Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1975922 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
83 lines
2.7 KiB
C
83 lines
2.7 KiB
C
/*
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* GK20A sema cmdbuf
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*
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* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/log.h>
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#include <nvgpu/nvgpu_mem.h>
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#include <nvgpu/semaphore.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/channel.h>
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#include "sema_cmdbuf_gk20a.h"
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u32 gk20a_get_sema_wait_cmd_size(void)
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{
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return 8U;
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}
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u32 gk20a_get_sema_incr_cmd_size(void)
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{
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return 10U;
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}
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void gk20a_add_sema_cmd(struct gk20a *g, struct nvgpu_semaphore *s,
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u64 sema_va, struct priv_cmd_entry *cmd,
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u32 off, bool acquire, bool wfi)
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{
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nvgpu_log_fn(g, " ");
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/* semaphore_a */
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nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010004U);
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/* offset_upper */
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nvgpu_mem_wr32(g, cmd->mem, off++, (u32)(sema_va >> 32) & 0xffU);
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/* semaphore_b */
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nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010005U);
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/* offset */
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nvgpu_mem_wr32(g, cmd->mem, off++, (u32)sema_va & 0xffffffff);
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if (acquire) {
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/* semaphore_c */
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nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010006U);
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/* payload */
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nvgpu_mem_wr32(g, cmd->mem, off++,
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nvgpu_semaphore_get_value(s));
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/* semaphore_d */
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nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010007U);
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/* operation: acq_geq, switch_en */
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nvgpu_mem_wr32(g, cmd->mem, off++, 0x4U | BIT32(12));
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} else {
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/* semaphore_c */
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nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010006U);
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/* payload */
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nvgpu_mem_wr32(g, cmd->mem, off++,
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nvgpu_semaphore_get_value(s));
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/* semaphore_d */
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nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010007U);
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/* operation: release, wfi */
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nvgpu_mem_wr32(g, cmd->mem, off++,
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0x2UL | ((wfi ? 0x0UL : 0x1UL) << 20));
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/* non_stall_int */
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nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010008U);
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/* ignored */
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nvgpu_mem_wr32(g, cmd->mem, off++, 0U);
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}
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} |