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fca82e45fb
Below HALs to get max FBPs, max LTC per FBP, max LTS pet LTC values are right now defined by GR unit. g->ops.gr.get_max_fbps_count() g->ops.gr.get_max_ltc_per_fbp() g->ops.gr.get_max_lts_per_ltc() These HALs only read registers from hw_top_*.h h/w unit, and as such belong to TOP unit. Move them appropriately as below g->ops.top.get_max_fbps_count() g->ops.top.get_max_ltc_per_fbp() g->ops.top.get_max_lts_per_ltc() Remove hw_top_*.h h/w header include from gr_gk20a.c and gr_gm20b.c Jira NVGPU-2894 Change-Id: I995d9f56edb65c9de98d2d15d34ecb72920a65c6 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2030672 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
52 lines
2.1 KiB
C
52 lines
2.1 KiB
C
/*
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* GM20B TOP UNIT
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*
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* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef TOP_GM20B_H
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#define TOP_GM20B_H
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#include <nvgpu/types.h>
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struct gk20a;
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struct nvgpu_device_info;
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int gm20b_device_info_parse_enum(struct gk20a *g, u32 table_entry,
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u32 *engine_id, u32 *runlist_id,
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u32 *intr_id, u32 *reset_id);
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int gm20b_device_info_parse_data(struct gk20a *g, u32 table_entry, u32 *inst_id,
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u32 *pri_base, u32 *fault_id);
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int gm20b_get_device_info(struct gk20a *g, struct nvgpu_device_info *dev_info,
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u32 engine_type, u32 inst_id);
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bool gm20b_is_engine_gr(struct gk20a *g, u32 engine_type);
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bool gm20b_is_engine_ce(struct gk20a *g, u32 engine_type);
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u32 gm20b_get_ce_inst_id(struct gk20a *g, u32 engine_type);
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u32 gm20b_top_get_max_gpc_count(struct gk20a *g);
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u32 gm20b_top_get_max_tpc_per_gpc_count(struct gk20a *g);
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u32 gm20b_top_get_max_fbps_count(struct gk20a *g);
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u32 gm20b_top_get_max_ltc_per_fbp(struct gk20a *g);
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u32 gm20b_top_get_max_lts_per_ltc(struct gk20a *g);
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#endif
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