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72de0a41b3
vgpu_mm_gp10b files contained gp10b specific code. - vgpu_gp10b_locked_gmmu_map function is common to all chips. Rename this function to vgpu_locked_gmmu_map and move this function implementation to to mm_vgpu file. - diable_bigpage variable is set to false in vgpu_gp10b_init_mm_setup_hw function. This is not related to mm hw initialization. Move this assignment to vgpu_init_variables along with other mm specific initialization as done for native. Change-Id: I4aba3096a3c945b8b3f4175382ebc78322e1d16e Signed-off-by: Aparna Das <aparnad@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2028862 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
66 lines
2.3 KiB
C
66 lines
2.3 KiB
C
/*
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* Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_MM_VGPU_H
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#define NVGPU_MM_VGPU_H
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struct nvgpu_mem;
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struct channel_gk20a;
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struct vm_gk20a_mapping_batch;
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struct gk20a_as_share;
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struct vm_gk20a;
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enum gk20a_mem_rw_flag;
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struct nvgpu_sgt;
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enum nvgpu_aperture;
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void vgpu_locked_gmmu_unmap(struct vm_gk20a *vm,
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u64 vaddr,
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u64 size,
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u32 pgsz_idx,
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bool va_allocated,
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enum gk20a_mem_rw_flag rw_flag,
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bool sparse,
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struct vm_gk20a_mapping_batch *batch);
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int vgpu_vm_bind_channel(struct vm_gk20a *vm,
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struct channel_gk20a *ch);
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int vgpu_mm_fb_flush(struct gk20a *g);
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void vgpu_mm_l2_invalidate(struct gk20a *g);
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int vgpu_mm_l2_flush(struct gk20a *g, bool invalidate);
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int vgpu_mm_tlb_invalidate(struct gk20a *g, struct nvgpu_mem *pdb);
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void vgpu_mm_mmu_set_debug_mode(struct gk20a *g, bool enable);
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u64 vgpu_locked_gmmu_map(struct vm_gk20a *vm,
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u64 map_offset,
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struct nvgpu_sgt *sgt,
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u64 buffer_offset,
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u64 size,
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u32 pgsz_idx,
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u8 kind_v,
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u32 ctag_offset,
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u32 flags,
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enum gk20a_mem_rw_flag rw_flag,
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bool clear_ctags,
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bool sparse,
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bool priv,
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struct vm_gk20a_mapping_batch *batch,
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enum nvgpu_aperture aperture);
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#endif /* NVGPU_MM_VGPU_H */
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