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git://nv-tegra.nvidia.com/linux-nvgpu.git
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30ea13e5e3
- rename vgpu_gr_gm20b_init_cyclestats() to vgpu_gr_init_cyclestats()
moving to gr_vgpu.c common to all vgpu chips.
- rename vgpu_gr_gp10b_init_ctxsw_preemption_mode() to
vgpu_gr_init_ctxsw_preemption_mode() moving to ctx_vgpu.c common
to all vgpu chips.
- rename vgpu_gr_gp10b_set_ctxsw_preemption_mode() to
vgpu_gr_set_ctxsw_preemption_mode() moving to ctx_vgpu.c common
to all vgpu chips.
- rename vgpu_gr_gp10b_set_preemption_mode() to
vgpu_gr_set_preemption_mode() moving to ctx_vgpu.c common
to all vgpu chips.
- rename vgpu_gr_gp10b_init_ctx_state() to vgpu_gr_init_ctx_state()
moving to ctx_vgpu.c common to all vgpu chips.
- combine vgpu_gr_gv11b_commit_ins() to vgpu_gr_commit_inst()
executing alloc/free subctx header code only if chip supports
subctx.
- remove inclusion of hw header files from vgpu gr code by
introducing hal ops for the following:
- alloc_global_ctx_buffers:
- hal op for getting global ctx cb buffer
- hal op for getting global ctx pagepool buffer size
- set_ctxsw_preemption_mode:
- hal op for getting ctx spill size
- hal op for getting ctx pagepool size
- hal op for getting ctx betacb size
- hal op for getting ctx attrib cb size
These chip specific function definitions are currently implemented in
chip specific gr files which will need to be moved to hal units.
Also use these hal ops for corresponding functions for native. This
makes gr_gv11b_set_ctxsw_preemption_mode() function redundant. Use
gr_gp10b_set_ctxsw_preemption_mode() for gv11b as well.
Jira GVSCI-334
Change-Id: I60be86f932e555176a972c125e3ea31270e6cba7
Signed-off-by: Aparna Das <aparnad@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2025428
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
144 lines
6.2 KiB
C
144 lines
6.2 KiB
C
/*
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* GP10B GPU GR
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*
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* Copyright (c) 2015-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_GR_GP10B_H
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#define NVGPU_GR_GP10B_H
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#include "gk20a/mm_gk20a.h"
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struct gk20a;
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struct gr_gk20a_isr_data;
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struct nvgpu_gr_ctx;
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struct nvgpu_preemption_modes_rec;
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struct gk20a_debug_output;
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#define PASCAL_CHANNEL_GPFIFO_A 0xC06FU
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#define PASCAL_A 0xC097U
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#define PASCAL_COMPUTE_A 0xC0C0U
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#define PASCAL_DMA_COPY_A 0xC0B5U
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#define PASCAL_DMA_COPY_B 0xC1B5U
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#define NVC097_SET_GO_IDLE_TIMEOUT 0x022cU
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#define NVC097_SET_ALPHA_CIRCULAR_BUFFER_SIZE 0x02dcU
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#define NVC097_SET_COALESCE_BUFFER_SIZE 0x1028U
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#define NVC097_SET_RD_COALESCE 0x102cU
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#define NVC097_SET_CIRCULAR_BUFFER_SIZE 0x1280U
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#define NVC097_SET_SHADER_EXCEPTIONS 0x1528U
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#define NVC097_SET_BES_CROP_DEBUG3 0x10c4U
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#define NVC097_SET_BES_CROP_DEBUG4 0x10b0U
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#define NVC0C0_SET_SHADER_EXCEPTIONS 0x1528U
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#define NVC0C0_SET_RD_COALESCE 0x0228U
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#define NVC097_BES_CROP_DEBUG4_CLAMP_FP_BLEND_TO_INF 0x0U
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#define NVC097_BES_CROP_DEBUG4_CLAMP_FP_BLEND_TO_MAXVAL 0x1U
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int gr_gp10b_init_fs_state(struct gk20a *g);
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void gr_gp10b_create_sysfs(struct gk20a *g);
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void gr_gp10b_remove_sysfs(struct gk20a *g);
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int gr_gp10b_handle_fecs_error(struct gk20a *g,
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struct channel_gk20a *__ch,
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struct gr_gk20a_isr_data *isr_data);
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int gr_gp10b_set_cilp_preempt_pending(struct gk20a *g,
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struct channel_gk20a *fault_ch);
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bool gr_gp10b_is_valid_class(struct gk20a *g, u32 class_num);
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bool gr_gp10b_is_valid_gfx_class(struct gk20a *g, u32 class_num);
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bool gr_gp10b_is_valid_compute_class(struct gk20a *g, u32 class_num);
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int gr_gp10b_handle_sm_exception(struct gk20a *g,
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u32 gpc, u32 tpc, u32 sm,
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bool *post_event, struct channel_gk20a *fault_ch,
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u32 *hww_global_esr);
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int gr_gp10b_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc,
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bool *post_event);
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int gr_gp10b_commit_global_cb_manager(struct gk20a *g,
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struct nvgpu_gr_ctx *gr_ctx, bool patch);
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void gr_gp10b_commit_global_pagepool(struct gk20a *g,
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struct nvgpu_gr_ctx *gr_ctx,
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u64 addr, u32 size, bool patch);
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u32 gr_gp10b_pagepool_default_size(struct gk20a *g);
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u32 gr_gp10b_calc_global_ctx_buffer_size(struct gk20a *g);
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void gr_gp10b_set_bes_crop_debug3(struct gk20a *g, u32 data);
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void gr_gp10b_set_bes_crop_debug4(struct gk20a *g, u32 data);
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int gr_gp10b_handle_sw_method(struct gk20a *g, u32 addr,
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u32 class_num, u32 offset, u32 data);
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void gr_gp10b_cb_size_default(struct gk20a *g);
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void gr_gp10b_set_alpha_circular_buffer_size(struct gk20a *g, u32 data);
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void gr_gp10b_set_circular_buffer_size(struct gk20a *g, u32 data);
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int gr_gp10b_init_ctx_state(struct gk20a *g);
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int gr_gp10b_set_ctxsw_preemption_mode(struct gk20a *g,
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struct nvgpu_gr_ctx *gr_ctx,
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struct vm_gk20a *vm, u32 class,
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u32 graphics_preempt_mode,
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u32 compute_preempt_mode);
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int gr_gp10b_init_ctxsw_preemption_mode(struct gk20a *g,
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struct nvgpu_gr_ctx *gr_ctx, struct vm_gk20a *vm,
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u32 class, u32 flags);
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void gr_gp10b_update_ctxsw_preemption_mode(struct gk20a *g,
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struct nvgpu_gr_ctx *gr_ctx, struct nvgpu_gr_subctx *subctx);
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int gr_gp10b_dump_gr_status_regs(struct gk20a *g,
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struct gk20a_debug_output *o);
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int gr_gp10b_wait_empty(struct gk20a *g);
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void gr_gp10b_commit_global_attrib_cb(struct gk20a *g,
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struct nvgpu_gr_ctx *gr_ctx,
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u64 addr, bool patch);
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void gr_gp10b_commit_global_bundle_cb(struct gk20a *g,
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struct nvgpu_gr_ctx *gr_ctx,
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u64 addr, u64 size, bool patch);
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int gr_gp10b_load_smid_config(struct gk20a *g);
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void gr_gp10b_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index);
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void gr_gp10b_get_access_map(struct gk20a *g,
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u32 **whitelist, int *num_entries);
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int gr_gp10b_pre_process_sm_exception(struct gk20a *g,
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u32 gpc, u32 tpc, u32 sm, u32 global_esr, u32 warp_esr,
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bool sm_debugger_attached, struct channel_gk20a *fault_ch,
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bool *early_exit, bool *ignore_debugger);
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u32 gp10b_gr_get_sm_hww_warp_esr(struct gk20a *g,
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u32 gpc, u32 tpc, u32 sm);
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u32 get_ecc_override_val(struct gk20a *g);
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int gr_gp10b_suspend_contexts(struct gk20a *g,
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struct dbg_session_gk20a *dbg_s,
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int *ctx_resident_ch_fd);
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int gr_gp10b_set_boosted_ctx(struct channel_gk20a *ch,
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bool boost);
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int gr_gp10b_set_preemption_mode(struct channel_gk20a *ch,
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u32 graphics_preempt_mode,
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u32 compute_preempt_mode);
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int gr_gp10b_get_preemption_mode_flags(struct gk20a *g,
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struct nvgpu_preemption_modes_rec *preemption_modes_rec);
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int gp10b_gr_fuse_override(struct gk20a *g);
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int gr_gp10b_init_preemption_state(struct gk20a *g);
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void gr_gp10b_set_preemption_buffer_va(struct gk20a *g,
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struct nvgpu_mem *mem, u64 gpu_va);
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int gr_gp10b_set_czf_bypass(struct gk20a *g, struct channel_gk20a *ch);
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void gr_gp10b_init_czf_bypass(struct gk20a *g);
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void gr_gp10b_init_gfxp_wfi_timeout_count(struct gk20a *g);
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unsigned long gr_gp10b_get_max_gfxp_wfi_timeout_count(struct gk20a *g);
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bool gr_gp10b_suspend_context(struct channel_gk20a *ch,
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bool *cilp_preempt_pending);
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u32 gp10b_gr_get_ctx_spill_size(struct gk20a *g);
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u32 gp10b_gr_get_ctx_pagepool_size(struct gk20a *g);
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u32 gp10b_gr_get_ctx_betacb_size(struct gk20a *g);
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u32 gp10b_gr_get_ctx_attrib_cb_size(struct gk20a *g, u32 betacb_size);
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#endif /* NVGPU_GR_GP10B_H */
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