mirror of
git://nv-tegra.nvidia.com/linux-nvgpu.git
synced 2025-12-24 02:22:34 +03:00
30ea13e5e3
- rename vgpu_gr_gm20b_init_cyclestats() to vgpu_gr_init_cyclestats()
moving to gr_vgpu.c common to all vgpu chips.
- rename vgpu_gr_gp10b_init_ctxsw_preemption_mode() to
vgpu_gr_init_ctxsw_preemption_mode() moving to ctx_vgpu.c common
to all vgpu chips.
- rename vgpu_gr_gp10b_set_ctxsw_preemption_mode() to
vgpu_gr_set_ctxsw_preemption_mode() moving to ctx_vgpu.c common
to all vgpu chips.
- rename vgpu_gr_gp10b_set_preemption_mode() to
vgpu_gr_set_preemption_mode() moving to ctx_vgpu.c common
to all vgpu chips.
- rename vgpu_gr_gp10b_init_ctx_state() to vgpu_gr_init_ctx_state()
moving to ctx_vgpu.c common to all vgpu chips.
- combine vgpu_gr_gv11b_commit_ins() to vgpu_gr_commit_inst()
executing alloc/free subctx header code only if chip supports
subctx.
- remove inclusion of hw header files from vgpu gr code by
introducing hal ops for the following:
- alloc_global_ctx_buffers:
- hal op for getting global ctx cb buffer
- hal op for getting global ctx pagepool buffer size
- set_ctxsw_preemption_mode:
- hal op for getting ctx spill size
- hal op for getting ctx pagepool size
- hal op for getting ctx betacb size
- hal op for getting ctx attrib cb size
These chip specific function definitions are currently implemented in
chip specific gr files which will need to be moved to hal units.
Also use these hal ops for corresponding functions for native. This
makes gr_gv11b_set_ctxsw_preemption_mode() function redundant. Use
gr_gp10b_set_ctxsw_preemption_mode() for gv11b as well.
Jira GVSCI-334
Change-Id: I60be86f932e555176a972c125e3ea31270e6cba7
Signed-off-by: Aparna Das <aparnad@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2025428
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
233 lines
10 KiB
C
233 lines
10 KiB
C
/*
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* GV11B GPU GR
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*
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* Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_GR_GV11B_H
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#define NVGPU_GR_GV11B_H
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#define EGPC_PRI_BASE 0x580000U
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#define EGPC_PRI_SHARED_BASE 0x480000U
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#define PRI_BROADCAST_FLAGS_SMPC BIT32(17)
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#define GFXP_WFI_TIMEOUT_UNIT_SYSCLK 0U
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#define GFXP_WFI_TIMEOUT_UNIT_USEC 1U
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struct gk20a;
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struct gr_gk20a;
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struct nvgpu_gr_ctx;
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struct nvgpu_warpstate;
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struct nvgpu_tsg_sm_error_state;
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struct gr_ctx_desc;
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struct gr_gk20a_isr_data;
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struct gk20a_debug_output;
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#define VOLTA_CHANNEL_GPFIFO_A 0xC36FU
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#define VOLTA_A 0xC397U
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#define VOLTA_COMPUTE_A 0xC3C0U
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#define VOLTA_DMA_COPY_A 0xC3B5U
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#define NVC397_SET_SHADER_EXCEPTIONS 0x1528U
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#define NVC397_SET_CIRCULAR_BUFFER_SIZE 0x1280U
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#define NVC397_SET_ALPHA_CIRCULAR_BUFFER_SIZE 0x02dcU
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#define NVC397_SET_GO_IDLE_TIMEOUT 0x022cU
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#define NVC397_SET_TEX_IN_DBG 0x10bcU
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#define NVC397_SET_SKEDCHECK 0x10c0U
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#define NVC397_SET_BES_CROP_DEBUG3 0x10c4U
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#define NVC397_SET_BES_CROP_DEBUG4 0x10b0U
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#define NVC397_SET_SHADER_CUT_COLLECTOR 0x10c8U
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#define NVC397_SET_TEX_IN_DBG_TSL1_RVCH_INVALIDATE BIT32(0)
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#define NVC397_SET_TEX_IN_DBG_SM_L1TAG_CTRL_CACHE_SURFACE_LD BIT32(1)
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#define NVC397_SET_TEX_IN_DBG_SM_L1TAG_CTRL_CACHE_SURFACE_ST BIT32(2)
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#define NVC397_SET_SKEDCHECK_18_MASK 0x3U
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#define NVC397_SET_SKEDCHECK_18_DEFAULT 0x0U
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#define NVC397_SET_SKEDCHECK_18_DISABLE 0x1U
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#define NVC397_SET_SKEDCHECK_18_ENABLE 0x2U
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#define NVC397_SET_SHADER_CUT_COLLECTOR_STATE_DISABLE 0x0U
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#define NVC397_SET_SHADER_CUT_COLLECTOR_STATE_ENABLE 0x1U
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#define NVC3C0_SET_SKEDCHECK 0x23cU
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#define NVC3C0_SET_SHADER_CUT_COLLECTOR 0x250U
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#define NVA297_SET_SHADER_EXCEPTIONS_ENABLE_FALSE U32(0)
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/*zcull*/
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void gr_gv11b_program_zcull_mapping(struct gk20a *g, u32 zcull_num_entries,
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u32 *zcull_map_tiles);
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void gr_gv11b_create_sysfs(struct gk20a *g);
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void gr_gv11b_remove_sysfs(struct gk20a *g);
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bool gr_gv11b_is_valid_class(struct gk20a *g, u32 class_num);
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bool gr_gv11b_is_valid_gfx_class(struct gk20a *g, u32 class_num);
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bool gr_gv11b_is_valid_compute_class(struct gk20a *g, u32 class_num);
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void gr_gv11b_enable_hww_exceptions(struct gk20a *g);
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void gr_gv11b_enable_exceptions(struct gk20a *g);
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int gr_gv11b_handle_tpc_sm_ecc_exception(struct gk20a *g,
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u32 gpc, u32 tpc,
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bool *post_event, struct channel_gk20a *fault_ch,
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u32 *hww_global_esr);
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int gr_gv11b_handle_gcc_exception(struct gk20a *g, u32 gpc, u32 tpc,
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bool *post_event, struct channel_gk20a *fault_ch,
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u32 *hww_global_esr);
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int gr_gv11b_handle_gpc_gpcmmu_exception(struct gk20a *g, u32 gpc,
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u32 gpc_exception);
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int gr_gv11b_handle_gpc_gpccs_exception(struct gk20a *g, u32 gpc,
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u32 gpc_exception);
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void gr_gv11b_enable_gpc_exceptions(struct gk20a *g);
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int gr_gv11b_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc,
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bool *post_event);
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u32 gr_gv11b_pagepool_default_size(struct gk20a *g);
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u32 gr_gv11b_calc_global_ctx_buffer_size(struct gk20a *g);
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int gr_gv11b_handle_sw_method(struct gk20a *g, u32 addr,
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u32 class_num, u32 offset, u32 data);
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void gr_gv11b_bundle_cb_defaults(struct gk20a *g);
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void gr_gv11b_cb_size_default(struct gk20a *g);
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void gr_gv11b_set_alpha_circular_buffer_size(struct gk20a *g, u32 data);
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void gr_gv11b_set_circular_buffer_size(struct gk20a *g, u32 data);
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int gr_gv11b_dump_gr_status_regs(struct gk20a *g,
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struct gk20a_debug_output *o);
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int gr_gv11b_wait_empty(struct gk20a *g);
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void gr_gv11b_commit_global_attrib_cb(struct gk20a *g,
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struct nvgpu_gr_ctx *gr_ctx,
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u64 addr, bool patch);
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void gr_gv11b_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index);
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void gr_gv11b_get_access_map(struct gk20a *g,
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u32 **whitelist, int *num_entries);
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int gr_gv11b_pre_process_sm_exception(struct gk20a *g,
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u32 gpc, u32 tpc, u32 sm, u32 global_esr, u32 warp_esr,
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bool sm_debugger_attached, struct channel_gk20a *fault_ch,
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bool *early_exit, bool *ignore_debugger);
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void gr_gv11b_fecs_host_int_enable(struct gk20a *g);
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int gr_gv11b_handle_fecs_error(struct gk20a *g,
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struct channel_gk20a *__ch,
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struct gr_gk20a_isr_data *isr_data);
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int gr_gv11b_setup_rop_mapping(struct gk20a *g, struct gr_gk20a *gr);
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int gr_gv11b_init_sw_veid_bundle(struct gk20a *g);
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void gr_gv11b_detect_sm_arch(struct gk20a *g);
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void gr_gv11b_program_sm_id_numbering(struct gk20a *g,
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u32 gpc, u32 tpc, u32 smid);
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int gr_gv11b_load_smid_config(struct gk20a *g);
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int gr_gv11b_commit_inst(struct channel_gk20a *c, u64 gpu_va);
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int gr_gv11b_commit_global_timeslice(struct gk20a *g, struct channel_gk20a *c);
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void gr_gv11b_load_tpc_mask(struct gk20a *g);
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void gr_gv11b_set_preemption_buffer_va(struct gk20a *g,
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struct nvgpu_mem *mem, u64 gpu_va);
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int gr_gv11b_init_fs_state(struct gk20a *g);
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void gv11b_gr_get_esr_sm_sel(struct gk20a *g, u32 gpc, u32 tpc,
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u32 *esr_sm_sel);
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int gv11b_gr_sm_trigger_suspend(struct gk20a *g);
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void gv11b_gr_bpt_reg_info(struct gk20a *g, struct nvgpu_warpstate *w_state);
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int gv11b_gr_set_sm_debug_mode(struct gk20a *g,
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struct channel_gk20a *ch, u64 sms, bool enable);
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int gv11b_gr_record_sm_error_state(struct gk20a *g, u32 gpc, u32 tpc, u32 sm,
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struct channel_gk20a *fault_ch);
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int gv11b_gr_clear_sm_error_state(struct gk20a *g,
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struct channel_gk20a *ch, u32 sm_id);
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void gv11b_gr_set_hww_esr_report_mask(struct gk20a *g);
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bool gv11b_gr_sm_debugger_attached(struct gk20a *g);
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void gv11b_gr_suspend_single_sm(struct gk20a *g,
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u32 gpc, u32 tpc, u32 sm,
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u32 global_esr_mask, bool check_errors);
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void gv11b_gr_suspend_all_sms(struct gk20a *g,
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u32 global_esr_mask, bool check_errors);
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void gv11b_gr_resume_single_sm(struct gk20a *g,
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u32 gpc, u32 tpc, u32 sm);
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void gv11b_gr_resume_all_sms(struct gk20a *g);
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int gv11b_gr_resume_from_pause(struct gk20a *g);
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u32 gv11b_gr_get_sm_hww_warp_esr(struct gk20a *g,
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u32 gpc, u32 tpc, u32 sm);
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u32 gv11b_gr_get_sm_hww_global_esr(struct gk20a *g,
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u32 gpc, u32 tpc, u32 sm);
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u32 gv11b_gr_get_sm_no_lock_down_hww_global_esr_mask(struct gk20a *g);
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int gv11b_gr_wait_for_sm_lock_down(struct gk20a *g,
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u32 gpc, u32 tpc, u32 sm,
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u32 global_esr_mask, bool check_errors);
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int gv11b_gr_lock_down_sm(struct gk20a *g,
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u32 gpc, u32 tpc, u32 sm, u32 global_esr_mask,
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bool check_errors);
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void gv11b_gr_clear_sm_hww(struct gk20a *g, u32 gpc, u32 tpc, u32 sm,
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u32 global_esr);
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int gr_gv11b_handle_tpc_mpc_exception(struct gk20a *g,
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u32 gpc, u32 tpc, bool *post_event);
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void gv11b_gr_init_ovr_sm_dsm_perf(void);
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void gv11b_gr_init_sm_dsm_reg_info(void);
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void gv11b_gr_get_sm_dsm_perf_regs(struct gk20a *g,
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u32 *num_sm_dsm_perf_regs,
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u32 **sm_dsm_perf_regs,
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u32 *perf_register_stride);
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void gv11b_gr_get_sm_dsm_perf_ctrl_regs(struct gk20a *g,
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u32 *num_sm_dsm_perf_ctrl_regs,
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u32 **sm_dsm_perf_ctrl_regs,
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u32 *ctrl_register_stride);
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void gv11b_gr_get_ovr_perf_regs(struct gk20a *g, u32 *num_ovr_perf_regs,
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u32 **ovr_perf_regs);
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void gv11b_gr_access_smpc_reg(struct gk20a *g, u32 quad, u32 offset);
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bool gv11b_gr_pri_is_egpc_addr(struct gk20a *g, u32 addr);
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bool gv11b_gr_pri_is_etpc_addr(struct gk20a *g, u32 addr);
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void gv11b_gr_get_egpc_etpc_num(struct gk20a *g, u32 addr,
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u32 *egpc_num, u32 *etpc_num);
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int gv11b_gr_decode_egpc_addr(struct gk20a *g, u32 addr,
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enum ctxsw_addr_type *addr_type, u32 *gpc_num, u32 *tpc_num,
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u32 *broadcast_flags);
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void gv11b_gr_egpc_etpc_priv_addr_table(struct gk20a *g, u32 addr,
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u32 gpc_num, u32 tpc_num, u32 broadcast_flags,
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u32 *priv_addr_table, u32 *t);
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u32 gv11b_gr_get_egpc_base(struct gk20a *g);
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void gr_gv11b_init_gpc_mmu(struct gk20a *g);
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int gr_gv11b_init_preemption_state(struct gk20a *g);
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void gr_gv11b_init_gfxp_wfi_timeout_count(struct gk20a *g);
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unsigned long gr_gv11b_get_max_gfxp_wfi_timeout_count(struct gk20a *g);
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void gr_gv11b_ecc_init_scrub_reg(struct gk20a *g);
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void gr_gv11b_update_ctxsw_preemption_mode(struct gk20a *g,
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struct nvgpu_gr_ctx *gr_ctx, struct nvgpu_gr_subctx *subctx);
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int gr_gv11b_handle_ssync_hww(struct gk20a *g);
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u32 gv11b_gr_sm_offset(struct gk20a *g, u32 sm);
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u32 gr_gv11b_get_pmm_per_chiplet_offset(void);
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int gr_gv11b_decode_priv_addr(struct gk20a *g, u32 addr,
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enum ctxsw_addr_type *addr_type,
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u32 *gpc_num, u32 *tpc_num, u32 *ppc_num, u32 *be_num,
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u32 *broadcast_flags);
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int gr_gv11b_create_priv_addr_table(struct gk20a *g,
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u32 addr,
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u32 *priv_addr_table,
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u32 *num_registers);
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u32 gr_gv11b_get_nonpes_aware_tpc(struct gk20a *g, u32 gpc, u32 tpc);
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void gr_gv11b_powergate_tpc(struct gk20a *g);
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void gr_gv11b_set_shader_cut_collector(struct gk20a *g, u32 data);
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void gv11b_gr_set_shader_exceptions(struct gk20a *g, u32 data);
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void gr_gv11b_set_skedcheck(struct gk20a *g, u32 data);
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void gr_gv11b_set_go_idle_timeout(struct gk20a *g, u32 data);
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void gr_gv11b_set_coalesce_buffer_size(struct gk20a *g, u32 data);
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void gr_gv11b_set_tex_in_dbg(struct gk20a *g, u32 data);
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u32 gv11b_gr_get_ctx_spill_size(struct gk20a *g);
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u32 gv11b_gr_get_ctx_pagepool_size(struct gk20a *g);
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u32 gv11b_gr_get_ctx_betacb_size(struct gk20a *g);
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u32 gv11b_gr_get_ctx_attrib_cb_size(struct gk20a *g, u32 betacb_size);
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#endif /* NVGPU_GR_GV11B_H */
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