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Subcontext PDBs and valid mask in the instance blocks of the channels in various subcontexts has to be updated when new subcontext is created or a subcontext is removed. Replayable fault state is cached in the channel structure. Replayable fault state for subcontext is set based on first channel's bind parameter. It was earlier programmed in function channel_setup_ramfc. init_inst_block_core is updated to setup TSG level pdb map and mask. Added new hal gv11b_channel_bind to enable the subcontext on channel bind. Bug 3677982 Change-Id: I58156c5b3ab6309b6a4b8e72b0e798d6a39c1bee Signed-off-by: Sagar Kamble <skamble@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2719994 Reviewed-by: Ankur Kishore <ankkishore@nvidia.com> GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
64 lines
2.0 KiB
C
64 lines
2.0 KiB
C
/*
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* Copyright (c) 2022, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_COMMON_FIFO_TSG_SUBCTX_PRIV_H
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#define NVGPU_COMMON_FIFO_TSG_SUBCTX_PRIV_H
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#include <nvgpu/types.h>
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#include <nvgpu/list.h>
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struct nvgpu_tsg;
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struct vm_gk20a;
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struct nvgpu_gr_subctx;
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struct nvgpu_tsg_subctx {
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/** Subcontext Id (aka. veid). */
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u32 subctx_id;
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/** TSG to which this subcontext belongs. */
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struct nvgpu_tsg *tsg;
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/** Subcontext's address space. */
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struct vm_gk20a *vm;
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/** Subcontext's GR ctx header and GR ctx buffers mappings. */
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struct nvgpu_gr_subctx *gr_subctx;
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/** Replayable faults state for a subcontext. */
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bool replayable;
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/**
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* Subcontext's entry in TSG's (#nvgpu_tsg) subcontexts list
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* #subctx_list.
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*/
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struct nvgpu_list_node tsg_entry;
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/**
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* List of channels (#nvgpu_channel) bound to this TSG subcontext.
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* Accessed by holding #ch_list_lock from TSG.
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*/
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struct nvgpu_list_node ch_list;
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};
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#endif /* NVGPU_COMMON_FIFO_TSG_SUBCTX_PRIV_H */
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