mirror of
git://nv-tegra.nvidia.com/linux-nvgpu.git
synced 2025-12-23 18:16:01 +03:00
a50aa08c0e
-Need to send clock frequency domain boardobj for PS3.5 -Need this to be sent before Clock fll boardobj is sent to PMU. JIRA NVGPU-1264 Change-Id: I66188b196929cc4d9d6ac3744a193b7075aa0327 Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1929787 Reviewed-on: https://git-master.nvidia.com/r/1950395 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
45 lines
1.6 KiB
C
45 lines
1.6 KiB
C
/*
|
|
* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
|
|
*
|
|
* Permission is hereby granted, free of charge, to any person obtaining a
|
|
* copy of this software and associated documentation files (the "Software"),
|
|
* to deal in the Software without restriction, including without limitation
|
|
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
|
* and/or sell copies of the Software, and to permit persons to whom the
|
|
* Software is furnished to do so, subject to the following conditions:
|
|
*
|
|
* The above copyright notice and this permission notice shall be included in
|
|
* all copies or substantial portions of the Software.
|
|
*
|
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
|
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
|
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
|
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
|
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
|
* DEALINGS IN THE SOFTWARE.
|
|
*/
|
|
|
|
#ifndef NVGPU_CLK_FREQ_DOMAIN_H
|
|
#define NVGPU_CLK_FREQ_DOMAIN_H
|
|
|
|
#include <nvgpu/pmuif/ctrlclk.h>
|
|
#include <nvgpu/pmuif/ctrlboardobj.h>
|
|
#include <nvgpu/pmuif/nvgpu_gpmu_cmdif.h>
|
|
#include <nvgpu/boardobjgrp_e32.h>
|
|
|
|
struct nvgpu_clk_freq_domain {
|
|
struct boardobj super;
|
|
u32 clk_domain;
|
|
};
|
|
|
|
struct nvgpu_clk_freq_domain_grp {
|
|
struct boardobjgrp_e32 super;
|
|
u32 init_flags;
|
|
};
|
|
|
|
int nvgpu_clk_freq_domain_sw_setup(struct gk20a *g);
|
|
int nvgpu_clk_freq_domain_pmu_setup(struct gk20a *g);
|
|
|
|
#endif /* NVGPU_CLK_FREQ_DOMAIN_H */
|