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The stored fence in struct gk20a_buffer_state is a post fence of a previous cde preparation job, if any. This stored fence is passed to userspace via NVGPU_GPU_IOCTL_PREPARE_COMPRESSIBLE_READ in case a preparation job was necessary to fulfill the request. As nothing else is needed from the fence, make it just a struct nvgpu_user_fence. Add nvgpu_user_fence_clone() for copying this user fence because it's stored internally and returned to userspace. The refcounted os fence needs special care. Now that the API is not so trivial anymore, add some documentation. Jira NVGPU-5248 Jira NVGPU-5493 Change-Id: I8bc4d52eaab7c7cbc5573b331e72e1d853f9f057 Signed-off-by: Konsta Hölttä <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2359065 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com> Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit
345 lines
8.5 KiB
C
345 lines
8.5 KiB
C
/*
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* Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/device.h>
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#include <linux/dma-buf.h>
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#include <linux/scatterlist.h>
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#include <nvgpu/comptags.h>
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#include <nvgpu/enabled.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/linux/vm.h>
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#include <nvgpu/bug.h>
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#include <nvgpu/fence.h>
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#include <nvgpu/vm.h>
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#include "platform_gk20a.h"
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#include "dmabuf_priv.h"
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#include "os_linux.h"
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#include "dmabuf_vidmem.h"
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void gk20a_mm_delete_priv(struct gk20a_dmabuf_priv *priv);
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enum nvgpu_aperture gk20a_dmabuf_aperture(struct gk20a *g,
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struct dma_buf *dmabuf)
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{
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#ifdef CONFIG_NVGPU_DGPU
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struct gk20a *buf_owner = nvgpu_vidmem_buf_owner(dmabuf);
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bool unified_memory = nvgpu_is_enabled(g, NVGPU_MM_UNIFIED_MEMORY);
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if (buf_owner == NULL) {
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/* Not nvgpu-allocated, assume system memory */
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return APERTURE_SYSMEM;
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} else if ((buf_owner == g) && unified_memory) {
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/* Looks like our video memory, but this gpu doesn't support
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* it. Warn about a bug and bail out */
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nvgpu_do_assert_print(g,
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"dmabuf is our vidmem but we don't have local vidmem");
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return APERTURE_INVALID;
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} else if (buf_owner != g) {
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/* Someone else's vidmem */
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return APERTURE_INVALID;
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} else {
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/* Yay, buf_owner == g */
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return APERTURE_VIDMEM;
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}
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#else
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return APERTURE_SYSMEM;
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#endif
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}
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static struct gk20a_dmabuf_priv *dma_buf_ops_to_gk20a_priv(
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struct dma_buf_ops *ops)
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{
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struct gk20a_dmabuf_priv *priv = container_of(ops,
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struct gk20a_dmabuf_priv, local_ops);
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return priv;
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}
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static void nvgpu_dma_buf_release(struct dma_buf *dmabuf)
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{
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struct gk20a_dmabuf_priv *priv = NULL;
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struct nvgpu_os_linux *l = NULL;
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priv = dma_buf_ops_to_gk20a_priv((struct dma_buf_ops *)dmabuf->ops);
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if (priv != NULL) {
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l = nvgpu_os_linux_from_gk20a(priv->g);
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} else {
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BUG();
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return;
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}
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/* remove this entry from the global tracking list */
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nvgpu_mutex_acquire(&l->dmabuf_priv_list_lock);
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gk20a_mm_delete_priv(priv);
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nvgpu_mutex_release(&l->dmabuf_priv_list_lock);
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dmabuf->ops->release(dmabuf);
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}
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int gk20a_dma_buf_set_drvdata(struct dma_buf *dmabuf, struct device *device,
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struct gk20a_dmabuf_priv *priv)
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{
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nvgpu_mutex_acquire(&priv->lock);
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priv->dmabuf = dmabuf;
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mutex_lock(&dmabuf->lock);
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priv->previous_ops = dmabuf->ops;
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/*
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* Make a copy of the original ops struct and then update the
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* release pointer
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*/
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priv->local_ops = *(dmabuf->ops);
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priv->local_ops.release = nvgpu_dma_buf_release;
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dmabuf->ops = &priv->local_ops;
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mutex_unlock(&dmabuf->lock);
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nvgpu_mutex_release(&priv->lock);
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return 0;
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}
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static struct gk20a_dmabuf_priv *gk20a_dmabuf_priv_from_list(
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struct nvgpu_list_node *node)
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{
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return container_of(node, struct gk20a_dmabuf_priv, list);
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}
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struct gk20a_dmabuf_priv *gk20a_dma_buf_get_drvdata(
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struct dma_buf *dmabuf, struct device *device)
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{
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struct gk20a_dmabuf_priv *priv = NULL;
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mutex_lock(&dmabuf->lock);
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if (dmabuf->ops->release == nvgpu_dma_buf_release) {
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priv = dma_buf_ops_to_gk20a_priv((struct dma_buf_ops *)dmabuf->ops);
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}
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mutex_unlock(&dmabuf->lock);
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return priv;
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}
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struct sg_table *nvgpu_mm_pin_privdata(struct device *dev,
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struct dma_buf *dmabuf, struct dma_buf_attachment **attachment)
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{
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struct gk20a *g = get_gk20a(dev);
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struct gk20a_dmabuf_priv *priv = NULL;
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priv = gk20a_dma_buf_get_drvdata(dmabuf, dev);
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if (!priv) {
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nvgpu_do_assert();
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return ERR_PTR(-EINVAL);
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}
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nvgpu_mutex_acquire(&priv->lock);
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if (priv->pin_count == 0) {
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priv->attach = dma_buf_attach(dmabuf, dev);
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if (IS_ERR(priv->attach)) {
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nvgpu_mutex_release(&priv->lock);
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nvgpu_err(g, "Failed to attach dma_buf (err = %ld)!",
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PTR_ERR(priv->attach));
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return ERR_CAST(priv->attach);
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}
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priv->sgt = dma_buf_map_attachment(priv->attach,
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DMA_BIDIRECTIONAL);
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if (IS_ERR(priv->sgt)) {
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dma_buf_detach(dmabuf, priv->attach);
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nvgpu_mutex_release(&priv->lock);
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nvgpu_err(g, "Failed to map attachment (err = %ld)!",
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PTR_ERR(priv->sgt));
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return ERR_CAST(priv->sgt);
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}
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}
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priv->pin_count++;
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nvgpu_mutex_release(&priv->lock);
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*attachment = priv->attach;
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return priv->sgt;
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}
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void nvgpu_mm_unpin_privdata(struct device *dev,
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struct dma_buf *dmabuf,
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struct dma_buf_attachment *attachment,
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struct sg_table *sgt)
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{
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struct gk20a_dmabuf_priv *priv = gk20a_dma_buf_get_drvdata(dmabuf, dev);
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dma_addr_t dma_addr;
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if (IS_ERR(priv) || !priv)
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return;
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nvgpu_mutex_acquire(&priv->lock);
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nvgpu_assert(priv->sgt == sgt);
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nvgpu_assert(priv->attach == attachment);
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priv->pin_count--;
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nvgpu_assert(priv->pin_count >= 0);
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dma_addr = sg_dma_address(priv->sgt->sgl);
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if (priv->pin_count == 0) {
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dma_buf_unmap_attachment(priv->attach, priv->sgt,
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DMA_BIDIRECTIONAL);
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dma_buf_detach(dmabuf, priv->attach);
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}
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nvgpu_mutex_release(&priv->lock);
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}
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/* This function must be called after acquiring the global level
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* dmabuf_priv_list_lock.
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*/
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void gk20a_mm_delete_priv(struct gk20a_dmabuf_priv *priv)
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{
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struct gk20a_buffer_state *s, *s_tmp;
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struct gk20a *g;
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struct dma_buf *dmabuf;
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if (!priv)
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return;
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g = priv->g;
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dmabuf = priv->dmabuf;
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if (priv->comptags.allocated && priv->comptags.lines) {
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WARN_ON(!priv->comptag_allocator);
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gk20a_comptaglines_free(priv->comptag_allocator,
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priv->comptags.offset,
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priv->comptags.lines);
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}
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/* Free buffer states */
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nvgpu_list_for_each_entry_safe(s, s_tmp, &priv->states,
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gk20a_buffer_state, list) {
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nvgpu_user_fence_release(&s->fence);
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nvgpu_list_del(&s->list);
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nvgpu_kfree(g, s);
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}
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/* The original pointer to dma_buf_ops is always put back here*/
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mutex_lock(&dmabuf->lock);
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dmabuf->ops = priv->previous_ops;
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mutex_unlock(&dmabuf->lock);
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/* Remove this entry from the global tracking list */
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nvgpu_list_del(&priv->list);
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nvgpu_kfree(g, priv);
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}
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void gk20a_dma_buf_priv_list_clear(struct nvgpu_os_linux *l)
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{
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struct gk20a_dmabuf_priv *priv, *priv_next;
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nvgpu_mutex_acquire(&l->dmabuf_priv_list_lock);
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nvgpu_list_for_each_entry_safe(priv, priv_next, &l->dmabuf_priv_list,
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gk20a_dmabuf_priv, list) {
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gk20a_mm_delete_priv(priv);
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}
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nvgpu_mutex_release(&l->dmabuf_priv_list_lock);
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}
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int gk20a_dmabuf_alloc_drvdata(struct dma_buf *dmabuf, struct device *dev)
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{
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struct gk20a *g = gk20a_get_platform(dev)->g;
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struct gk20a_dmabuf_priv *priv;
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struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
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priv = gk20a_dma_buf_get_drvdata(dmabuf, dev);
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if (likely(priv))
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return 0;
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nvgpu_mutex_acquire(&g->mm.priv_lock);
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priv = gk20a_dma_buf_get_drvdata(dmabuf, dev);
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if (priv)
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goto priv_exist_or_err;
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priv = nvgpu_kzalloc(g, sizeof(*priv));
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if (!priv) {
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priv = ERR_PTR(-ENOMEM);
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goto priv_exist_or_err;
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}
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nvgpu_mutex_init(&priv->lock);
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nvgpu_init_list_node(&priv->states);
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priv->g = g;
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gk20a_dma_buf_set_drvdata(dmabuf, dev, priv);
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nvgpu_init_list_node(&priv->list);
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/* Append this priv to the global tracker */
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nvgpu_mutex_acquire(&l->dmabuf_priv_list_lock);
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nvgpu_list_add_tail(&l->dmabuf_priv_list, &priv->list);
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nvgpu_mutex_release(&l->dmabuf_priv_list_lock);
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priv_exist_or_err:
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nvgpu_mutex_release(&g->mm.priv_lock);
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if (IS_ERR(priv))
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return -ENOMEM;
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return 0;
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}
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int gk20a_dmabuf_get_state(struct dma_buf *dmabuf, struct gk20a *g,
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u64 offset, struct gk20a_buffer_state **state)
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{
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int err = 0;
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struct gk20a_dmabuf_priv *priv;
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struct gk20a_buffer_state *s;
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struct device *dev = dev_from_gk20a(g);
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if (offset >= (u64)dmabuf->size) {
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nvgpu_do_assert();
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return -EINVAL;
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}
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err = gk20a_dmabuf_alloc_drvdata(dmabuf, dev);
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if (err)
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return err;
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priv = gk20a_dma_buf_get_drvdata(dmabuf, dev);
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if (!priv) {
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nvgpu_do_assert();
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return -ENOSYS;
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}
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nvgpu_mutex_acquire(&priv->lock);
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nvgpu_list_for_each_entry(s, &priv->states, gk20a_buffer_state, list)
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if (s->offset == offset)
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goto out;
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/* State not found, create state. */
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s = nvgpu_kzalloc(g, sizeof(*s));
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if (!s) {
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err = -ENOMEM;
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goto out;
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}
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s->offset = offset;
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nvgpu_init_list_node(&s->list);
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nvgpu_mutex_init(&s->lock);
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nvgpu_list_add_tail(&s->list, &priv->states);
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out:
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nvgpu_mutex_release(&priv->lock);
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if (!err)
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*state = s;
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return err;
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}
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