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b2345cd01a
- Add support for unit tests to run on orin platform. JIRA NVGPU-9909 Change-Id: If4ca69b77d0d8483c0e9f6a6a5a64c3c3e050d65 Signed-off-by: srajum <srajum@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2737876 Reviewed-by: Dinesh T <dt@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> Reviewed-by: Ankur Kishore <ankkishore@nvidia.com> GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
224 lines
6.6 KiB
C
224 lines
6.6 KiB
C
/*
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* Copyright (c) 2018-2023, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <unit/io.h>
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#include <unit/unit.h>
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#include <nvgpu/posix/io.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/hal_init.h>
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#include <nvgpu/enabled.h>
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#include <common/gr/gr_priv.h>
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#include "nvgpu-fuse.h"
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#include "nvgpu-fuse-priv.h"
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#include "nvgpu-fuse-gp10b.h"
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#include "nvgpu-fuse-gm20b.h"
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#include "common/gr/gr_config_priv.h"
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#ifdef CONFIG_NVGPU_DGPU
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#include "nvgpu-fuse-tu104.h"
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#endif
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#define NV_PMC_BOOT_0_ARCHITECTURE_GV110 (0x00000015 << \
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NVGPU_GPU_ARCHITECTURE_SHIFT)
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#define NV_PMC_BOOT_0_ARCHITECTURE_GA100 (0x00000017 << \
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NVGPU_GPU_ARCHITECTURE_SHIFT)
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#define NV_PMC_BOOT_0_IMPLEMENTATION_B 0xB
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/*
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* Mock I/O
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*/
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/*
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* Write callback. Forward the write access to the mock IO framework.
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*/
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static void writel_access_reg_fn(struct gk20a *g,
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struct nvgpu_reg_access *access)
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{
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nvgpu_posix_io_writel_reg_space(g, access->addr, access->value);
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}
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/*
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* Read callback. Get the register value from the mock IO framework.
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*/
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static void readl_access_reg_fn(struct gk20a *g,
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struct nvgpu_reg_access *access)
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{
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access->value = nvgpu_posix_io_readl_reg_space(g, access->addr);
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}
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static struct nvgpu_posix_io_callbacks test_reg_callbacks = {
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/* Write APIs all can use the same accessor. */
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.writel = writel_access_reg_fn,
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.writel_check = writel_access_reg_fn,
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.bar1_writel = writel_access_reg_fn,
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.usermode_writel = writel_access_reg_fn,
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/* Likewise for the read APIs. */
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.__readl = readl_access_reg_fn,
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.readl = readl_access_reg_fn,
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.bar1_readl = readl_access_reg_fn,
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};
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/*
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* Overrides for the fuse functionality
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*/
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u32 gcplex_config;
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/* Return pass and value for reading gcplex */
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int read_gcplex_config_fuse_pass(struct gk20a *g, u32 *val)
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{
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*val = gcplex_config;
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return 0;
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}
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/* Return fail for reading gcplex */
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int read_gcplex_config_fuse_fail(struct gk20a *g, u32 *val)
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{
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return -ENODEV;
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}
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int test_fuse_device_common_init(struct unit_module *m,
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struct gk20a *g, void *__args)
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{
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int ret = UNIT_SUCCESS;
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int result;
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struct fuse_test_args *args = (struct fuse_test_args *)__args;
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struct nvgpu_gr gr = {0};
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struct nvgpu_gr_config config = {0};
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/* Create fuse register space */
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if (nvgpu_posix_io_add_reg_space(g, args->fuse_base_addr, 0x1fff) != 0) {
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unit_err(m, "%s: failed to create register space\n",
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__func__);
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return UNIT_FAIL;
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}
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(void)nvgpu_posix_register_io(g, &test_reg_callbacks);
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#ifdef CONFIG_NVGPU_HAL_NON_FUSA
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g->params.gpu_arch = args->gpu_arch << NVGPU_GPU_ARCHITECTURE_SHIFT;
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g->params.gpu_impl = args->gpu_impl;
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#else
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if (strcmp(g->name, "ga10b") == 0) {
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g->params.gpu_arch = NV_PMC_BOOT_0_ARCHITECTURE_GA100;
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} else {
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g->params.gpu_arch = NV_PMC_BOOT_0_ARCHITECTURE_GV110;
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}
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g->params.gpu_impl = NV_PMC_BOOT_0_IMPLEMENTATION_B;
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#endif
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g->gr = &gr;
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gr.config = &config;
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nvgpu_posix_io_writel_reg_space(g, args->sec_fuse_addr, 0x0);
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result = nvgpu_init_hal(g);
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if (result != 0) {
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unit_err(m, "%s: nvgpu_init_hal returned error %d\n",
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__func__, result);
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ret = UNIT_FAIL;
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}
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g->ops.fuse.read_gcplex_config_fuse = read_gcplex_config_fuse_pass;
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nvgpu_posix_io_writel_reg_space(g, GM20B_TOP_NUM_GPCS,
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GM20B_MAX_GPC_COUNT);
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return ret;
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}
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int test_fuse_device_common_cleanup(struct unit_module *m,
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struct gk20a *g, void *__args)
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{
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struct fuse_test_args *args = (struct fuse_test_args *)__args;
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nvgpu_posix_io_delete_reg_space(g, args->fuse_base_addr);
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return 0;
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}
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struct unit_module_test fuse_tests[] = {
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UNIT_TEST(fuse_gp10b_init, test_fuse_device_common_init,
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&gp10b_init_args, 0),
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UNIT_TEST(fuse_gp10b_check_sec, test_fuse_gp10b_check_sec, NULL, 0),
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UNIT_TEST(fuse_gp10b_check_gcplex_fail,
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test_fuse_gp10b_check_gcplex_fail,
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NULL,
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0),
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UNIT_TEST(fuse_gp10b_check_sec_invalid_gcplex,
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test_fuse_gp10b_check_sec_invalid_gcplex,
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NULL,
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0),
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UNIT_TEST(fuse_gp10b_check_non_sec,
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test_fuse_gp10b_check_non_sec,
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NULL,
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0),
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UNIT_TEST(fuse_gp10b_ecc, test_fuse_gp10b_ecc, NULL, 0),
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UNIT_TEST(fuse_gp10b_feature_override_disable,
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test_fuse_gp10b_feature_override_disable, NULL, 0),
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#ifdef CONFIG_NVGPU_SIM
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UNIT_TEST(fuse_gp10b_check_fmodel, test_fuse_gp10b_check_fmodel, NULL, 0),
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#endif
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UNIT_TEST(fuse_gp10b_cleanup, test_fuse_device_common_cleanup,
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&gp10b_init_args, 0),
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UNIT_TEST(fuse_gm20b_init, test_fuse_device_common_init,
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&gm20b_init_args, 0),
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#ifdef CONFIG_NVGPU_HAL_NON_FUSA
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UNIT_TEST(fuse_gm20b_check_sec, test_fuse_gm20b_check_sec, NULL, 0),
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UNIT_TEST(fuse_gm20b_check_sec_invalid_gcplex,
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test_fuse_gm20b_check_sec_invalid_gcplex,
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NULL,
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0),
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UNIT_TEST(fuse_gm20b_check_gcplex_fail,
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test_fuse_gm20b_check_gcplex_fail,
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NULL,
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0),
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UNIT_TEST(fuse_gm20b_check_non_sec,
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test_fuse_gm20b_check_non_sec,
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NULL,
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0),
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#endif
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UNIT_TEST(fuse_gm20b_basic_fuses, test_fuse_gm20b_basic_fuses, NULL, 0),
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UNIT_TEST(test_fuse_gm20b_basic_fuses_bvec, test_fuse_gm20b_basic_fuses_bvec, NULL, 0),
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#ifdef CONFIG_NVGPU_SIM
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UNIT_TEST(fuse_gm20b_check_fmodel, test_fuse_gm20b_check_fmodel, NULL, 0),
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#endif
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UNIT_TEST(fuse_gm20b_cleanup, test_fuse_device_common_cleanup,
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&gm20b_init_args, 0),
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#ifdef CONFIG_NVGPU_DGPU
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UNIT_TEST(fuse_tu104_init, test_fuse_device_common_init,
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&tu104_init_args, 0),
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UNIT_TEST(fuse_tu104_vin_cal_rev, test_fuse_tu104_vin_cal_rev, NULL, 0),
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UNIT_TEST(fuse_tu104_vin_cal_slope_intercept,
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test_fuse_tu104_vin_cal_slope_intercept,
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NULL,
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0),
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UNIT_TEST(fuse_tu104_cleanup, test_fuse_device_common_cleanup,
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&tu104_init_args, 0),
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#endif
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};
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UNIT_MODULE(fuse, fuse_tests, UNIT_PRIO_NVGPU_TEST);
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