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147564cbd5
Changes: - Send down BOARDOBJGRP classId to the PMU. Assign each BOARDOBJ the classId of its parent group which is set to zero in current implementation. Changed in NVGPU to send board obj grp classid to PMU. - Disable IPC VMIN support as pmu-tu10a profile doesn't support. - Change in clk vf point enumeration types. - Change in pstate type values. - Updated ctrl_perf_vfe_var_single_sensed_fuse_ver_vfield_info NVGPU-PMU interface struct with b_ver_expected_is_mask to send whether the expected version is single value or should be interpreted as a bit mask with bits corresponding to expected versions set. NVBUG-200593676 NVGPU-5066 Change-Id: I17b172d88f8b74fbf78044caf7f64cd8811f9fb7 Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2308533 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com> Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
55 lines
1.8 KiB
C
55 lines
1.8 KiB
C
/*
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* general p state infrastructure
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*
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* Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_PERF_PSTATE_H
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#define NVGPU_PERF_PSTATE_H
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#define CTRL_PERF_PSTATE_TYPE_35 0x04U
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struct pstate_clk_info_list {
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u32 num_info;
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struct nvgpu_pmu_perf_pstate_clk_info clksetinfo[CLK_SET_INFO_MAX_SIZE];
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};
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struct pstates {
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struct boardobjgrp_e32 super;
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u8 num_clk_domains;
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};
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struct pstate {
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struct boardobj super;
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u32 num;
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u8 lpwr_entry_idx;
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u32 flags;
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u8 pcie_idx;
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u8 nvlink_idx;
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struct pstate_clk_info_list clklist;
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};
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int perf_pstate_sw_setup(struct gk20a *g);
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int perf_pstate_pmu_setup(struct gk20a *g);
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int perf_pstate_get_table_entry_idx(struct gk20a *g, u32 num);
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#endif /* NVGPU_PERF_PSTATE_H */
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