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b3d16b23d5
Move private command buffer related functionality to priv_cmdbuf.c. This is used only for kernel mode submits, so it makes sense to group it out, and the priv cmdbuf stuff is used also by things that don't care about channels. Jira NVGPU-4548 Change-Id: Idbb42e3ed3984e16c654bb9aa2b7564b780048a4 Signed-off-by: Konsta Hölttä <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2323146 (cherry picked from commit bb67bfc7ab8e87236f31bc4f6c80dab042609f21) Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2328406 Reviewed-by: automaticguardword <automaticguardword@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
85 lines
2.7 KiB
C
85 lines
2.7 KiB
C
/*
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* GK20A sema cmdbuf
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*
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* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/log.h>
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#include <nvgpu/nvgpu_mem.h>
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#include <nvgpu/semaphore.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/channel.h>
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#include <nvgpu/priv_cmdbuf.h>
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#include "sema_cmdbuf_gk20a.h"
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u32 gk20a_sema_get_wait_cmd_size(void)
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{
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return 8U;
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}
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u32 gk20a_sema_get_incr_cmd_size(void)
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{
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return 10U;
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}
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void gk20a_sema_add_cmd(struct gk20a *g, struct nvgpu_semaphore *s,
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u64 sema_va, struct priv_cmd_entry *cmd,
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u32 off, bool acquire, bool wfi)
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{
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nvgpu_log_fn(g, " ");
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/* semaphore_a */
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nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010004U);
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/* offset_upper */
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nvgpu_mem_wr32(g, cmd->mem, off++, (u32)(sema_va >> 32) & 0xffU);
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/* semaphore_b */
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nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010005U);
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/* offset */
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nvgpu_mem_wr32(g, cmd->mem, off++, (u32)sema_va & 0xffffffff);
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if (acquire) {
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/* semaphore_c */
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nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010006U);
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/* payload */
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nvgpu_mem_wr32(g, cmd->mem, off++,
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nvgpu_semaphore_get_value(s));
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/* semaphore_d */
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nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010007U);
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/* operation: acq_geq, switch_en */
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nvgpu_mem_wr32(g, cmd->mem, off++, 0x4U | BIT32(12));
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} else {
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/* semaphore_c */
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nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010006U);
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/* payload */
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nvgpu_mem_wr32(g, cmd->mem, off++,
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nvgpu_semaphore_get_value(s));
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/* semaphore_d */
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nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010007U);
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/* operation: release, wfi */
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nvgpu_mem_wr32(g, cmd->mem, off++,
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0x2UL | ((wfi ? 0x0UL : 0x1UL) << 20));
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/* non_stall_int */
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nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010008U);
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/* ignored */
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nvgpu_mem_wr32(g, cmd->mem, off++, 0U);
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}
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}
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