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d916e85171
Split out the max value increment and syncpt interrupt registration out of nvgpu_channel_sync_incr*(). This API is called in the submit path to prepare buffers and tracking resources, but later on in the submit path errors can still occur so that the increment wouldn't happen (unless artificially forced by sw). The increment and irq registration cannot easily be undone and it makes more sense to do these at the moment when the prepared job is finally ready, so add a new nvgpu_channel_sync_mark_progress() API to be called later in the submit path to signal that progress shall eventually happen on the sync. Without this, the max value would stay too large after an unsuccessful submit until the channel gets closed. The sync object (syncpt or semaphore) is always exclusively owned by the channel that allocated it, so nonatomically reading the max value first in sync_incr() and incrementing it later in mark_progress() is racefree; all submits per channel are serialized. Change the channel syncpoint to client managed from host managed so that nvhost-exported sync fences behave correctly with the temporary state where the fence threshold is over the max value. Ideally we'd always track nvgpu-owned syncpts' max values internally, but this is enough for now. Jira NVGPU-5491 Change-Id: Idf0bda7ac93d7f2f114cdeb497fe6b5369d21c95 Signed-off-by: Konsta Hölttä <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2340465 Reviewed-by: automaticguardword <automaticguardword@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
105 lines
3.2 KiB
C
105 lines
3.2 KiB
C
/*
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* GK20A Channel Synchronization Abstraction
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*
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* Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/kmem.h>
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#include <nvgpu/log.h>
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#include <nvgpu/atomic.h>
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#include <nvgpu/bug.h>
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#include <nvgpu/list.h>
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#include <nvgpu/nvhost.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/os_fence.h>
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#include <nvgpu/os_fence_syncpts.h>
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#include <nvgpu/os_fence_semas.h>
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#include <nvgpu/channel.h>
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#include <nvgpu/channel_sync.h>
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#include <nvgpu/channel_sync_syncpt.h>
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#include <nvgpu/channel_sync_semaphore.h>
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#include <nvgpu/fence.h>
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#include "channel_sync_priv.h"
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struct nvgpu_channel_sync *nvgpu_channel_sync_create(struct nvgpu_channel *c)
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{
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if (nvgpu_has_syncpoints(c->g)) {
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return nvgpu_channel_sync_syncpt_create(c);
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} else {
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#ifdef CONFIG_NVGPU_SW_SEMAPHORE
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return nvgpu_channel_sync_semaphore_create(c);
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#else
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return NULL;
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#endif
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}
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}
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bool nvgpu_channel_sync_needs_os_fence_framework(struct gk20a *g)
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{
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return !nvgpu_has_syncpoints(g);
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}
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int nvgpu_channel_sync_wait_fence_fd(struct nvgpu_channel_sync *s, int fd,
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struct priv_cmd_entry **entry, u32 max_wait_cmds)
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{
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return s->ops->wait_fence_fd(s, fd, entry, max_wait_cmds);
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}
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int nvgpu_channel_sync_incr(struct nvgpu_channel_sync *s,
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struct priv_cmd_entry **entry, struct nvgpu_fence_type *fence,
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bool need_sync_fence)
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{
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return s->ops->incr(s, entry, fence, need_sync_fence);
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}
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int nvgpu_channel_sync_incr_user(struct nvgpu_channel_sync *s,
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struct priv_cmd_entry **entry, struct nvgpu_fence_type *fence,
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bool wfi, bool need_sync_fence)
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{
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return s->ops->incr_user(s, entry, fence, wfi, need_sync_fence);
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}
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void nvgpu_channel_sync_mark_progress(struct nvgpu_channel_sync *s,
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bool register_irq)
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{
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s->ops->mark_progress(s, register_irq);
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}
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void nvgpu_channel_sync_set_min_eq_max(struct nvgpu_channel_sync *s)
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{
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s->ops->set_min_eq_max(s);
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}
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void nvgpu_channel_sync_get_ref(struct nvgpu_channel_sync *s)
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{
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nvgpu_atomic_inc(&s->refcount);
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}
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bool nvgpu_channel_sync_put_ref_and_check(struct nvgpu_channel_sync *s)
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{
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return nvgpu_atomic_dec_and_test(&s->refcount);
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}
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void nvgpu_channel_sync_destroy(struct nvgpu_channel_sync *sync)
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{
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sync->ops->destroy(sync);
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}
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