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git://nv-tegra.nvidia.com/linux-nvgpu.git
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e81a36e56a
It's preparing to add bellow CFLAGS:
-Werror -Wall -Wextra \
-Wmissing-braces -Wpointer-arith -Wundef \
-Wconversion -Wsign-conversion \
-Wformat-security \
-Wmissing-declarations -Wredundant-decls -Wimplicit-fallthrough
Jira GVSCI-11640
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Change-Id: Ia16ef186da1e97badff9dd0bf8cbd6700dd77b15
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2555057
Reviewed-by: Shashank Singh <shashsingh@nvidia.com>
Reviewed-by: Aparna Das <aparnad@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
95 lines
3.2 KiB
C
95 lines
3.2 KiB
C
/*
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* GK20A USERD
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*
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* Copyright (c) 2011-2022, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/bug.h>
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#include <nvgpu/channel.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/io.h>
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#include <nvgpu/nvgpu_mem.h>
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#include "userd_gk20a.h"
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#include <nvgpu/hw/gk20a/hw_ram_gk20a.h>
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#ifdef CONFIG_NVGPU_USERD
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void gk20a_userd_init_mem(struct gk20a *g, struct nvgpu_channel *c)
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{
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struct nvgpu_mem *mem = c->userd_mem;
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u32 offset = c->userd_offset / U32(sizeof(u32));
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nvgpu_log_fn(g, " ");
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nvgpu_mem_wr32(g, mem, offset + ram_userd_put_w(), 0);
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nvgpu_mem_wr32(g, mem, offset + ram_userd_get_w(), 0);
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nvgpu_mem_wr32(g, mem, offset + ram_userd_ref_w(), 0);
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nvgpu_mem_wr32(g, mem, offset + ram_userd_put_hi_w(), 0);
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nvgpu_mem_wr32(g, mem, offset + ram_userd_gp_top_level_get_w(), 0);
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nvgpu_mem_wr32(g, mem, offset + ram_userd_gp_top_level_get_hi_w(), 0);
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nvgpu_mem_wr32(g, mem, offset + ram_userd_get_hi_w(), 0);
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nvgpu_mem_wr32(g, mem, offset + ram_userd_gp_get_w(), 0);
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nvgpu_mem_wr32(g, mem, offset + ram_userd_gp_put_w(), 0);
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}
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#ifdef CONFIG_NVGPU_KERNEL_MODE_SUBMIT
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u32 gk20a_userd_gp_get(struct gk20a *g, struct nvgpu_channel *c)
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{
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u64 userd_gpu_va = nvgpu_channel_userd_gpu_va(c);
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u64 addr = userd_gpu_va + sizeof(u32) * ram_userd_gp_get_w();
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BUG_ON(u64_hi32(addr) != 0U);
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return nvgpu_bar1_readl(g, (u32)addr);
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}
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u64 gk20a_userd_pb_get(struct gk20a *g, struct nvgpu_channel *c)
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{
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u64 userd_gpu_va = nvgpu_channel_userd_gpu_va(c);
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u64 lo_addr = userd_gpu_va + sizeof(u32) * ram_userd_get_w();
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u64 hi_addr = userd_gpu_va + sizeof(u32) * ram_userd_get_hi_w();
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u32 lo, hi;
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BUG_ON((u64_hi32(lo_addr) != 0U) || (u64_hi32(hi_addr) != 0U));
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lo = nvgpu_bar1_readl(g, (u32)lo_addr);
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hi = nvgpu_bar1_readl(g, (u32)hi_addr);
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return ((u64)hi << 32) | lo;
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}
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void gk20a_userd_gp_put(struct gk20a *g, struct nvgpu_channel *c)
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{
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u64 userd_gpu_va = nvgpu_channel_userd_gpu_va(c);
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u64 addr = userd_gpu_va + sizeof(u32) * ram_userd_gp_put_w();
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BUG_ON(u64_hi32(addr) != 0U);
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nvgpu_bar1_writel(g, (u32)addr, c->gpfifo.put);
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}
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#endif
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#endif /* CONFIG_NVGPU_USERD */
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u32 gk20a_userd_entry_size(struct gk20a *g)
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{
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(void)g;
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return BIT32(ram_userd_base_shift_v());
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}
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