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git://nv-tegra.nvidia.com/linux-nvgpu.git
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b4528cac93
API nvgpu_get_timestamps_zipper() returning with power reference in case of failure. Patch corrects the sequence. Bug 3412554 Change-Id: Id5bd027fd9861d2b04341b5045326278cef5c5d1 Signed-off-by: Prateek sethi <prsethi@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2551274 Reviewed-by: svcacv <svcacv@nvidia.com> Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit
106 lines
2.8 KiB
C
106 lines
2.8 KiB
C
/*
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* Copyright (c) 2017-2021, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/ptimer.h>
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#include <nvgpu/gk20a.h>
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#ifdef CONFIG_NVGPU_IOCTL_NON_FUSA
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#include <nvgpu/timers.h>
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#include <nvgpu/nvgpu_init.h>
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#include <nvgpu/power_features/cg.h>
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#endif
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static u32 ptimer_scalingfactor10x(u32 ptimer_src_freq)
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{
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return nvgpu_safe_cast_u64_to_u32((U64(PTIMER_REF_FREQ_HZ) * U64(10))
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/ U64(ptimer_src_freq));
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}
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int nvgpu_ptimer_scale(struct gk20a *g, u32 timeout, u32 *scaled_timeout)
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{
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u32 scale10x;
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/* Validate the input parameters */
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if (scaled_timeout == NULL) {
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return -EINVAL;
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}
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if (timeout > U32_MAX / 10U) {
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return -EINVAL;
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}
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/* Calculate the scaling factor */
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if (g->ptimer_src_freq == 0U) {
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return -EINVAL;
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}
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scale10x = ptimer_scalingfactor10x(g->ptimer_src_freq);
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if (scale10x == 0U) {
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return -EINVAL;
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}
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/* Scale the timeout value */
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if (((timeout * 10U) % scale10x) >= (scale10x / 2U)) {
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*scaled_timeout = ((timeout * 10U) / scale10x) + 1U;
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} else {
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*scaled_timeout = (timeout * 10U) / scale10x;
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}
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return 0;
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}
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#ifdef CONFIG_NVGPU_IOCTL_NON_FUSA
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int nvgpu_ptimer_init(struct gk20a *g)
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{
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#if defined(CONFIG_NVGPU_NON_FUSA)
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nvgpu_cg_slcg_timer_load_enable(g);
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#endif
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return 0;
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}
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int nvgpu_get_timestamps_zipper(struct gk20a *g,
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u32 source_id, u32 count,
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struct nvgpu_cpu_time_correlation_sample *samples)
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{
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int err = 0;
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unsigned int i = 0;
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if (gk20a_busy(g) != 0) {
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nvgpu_err(g, "GPU not powered on\n");
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err = -EINVAL;
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return err;
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}
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for (i = 0; i < count; i++) {
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err = g->ops.ptimer.read_ptimer(g, &samples[i].gpu_timestamp);
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if (err != 0) {
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goto idle;
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}
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samples[i].cpu_timestamp = nvgpu_hr_timestamp();
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}
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idle:
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gk20a_idle(g);
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return err;
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}
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#endif
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