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eb690cb391
Support added to send PMU and FECS signatures to ACR ucode Bug 200046413 Change-Id: Ie1babb640be20a697ad4d6dd18bd11161edb263c Signed-off-by: Vijayakumar <vsubbu@nvidia.com> Signed-off-by: Supriya <ssharatkumar@nvidia.com> Signed-off-by: Vijayakumar <vsubbu@nvidia.com>
402 lines
13 KiB
C
402 lines
13 KiB
C
/*
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* GM20B ACR
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*
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* Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#ifndef __ACR_GM20B_H_
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#define __ACR_GM20B_H_
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#include "gk20a/gk20a.h"
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#include "mm_gm20b.h"
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/*Defines*/
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/*chip specific defines*/
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#define MAX_SUPPORTED_LSFM 2 /*PMU, FECS, GPCCS*/
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#define LSF_UCODE_DATA_ALIGNMENT 4096
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#define GM20B_PMU_UCODE_IMAGE "gpmu_ucode_image.bin"
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#define GM20B_PMU_UCODE_DESC "gpmu_ucode_desc.bin"
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#define GM20B_HSBIN_PMU_UCODE_IMAGE "acr_ucode.bin"
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#define GM20B_HSBIN_PMU_BL_UCODE_IMAGE "pmu_bl.bin"
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#define GM20B_PMU_UCODE_SIG "pmu_sig.bin"
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#define GM20B_FECS_UCODE_SIG "fecs_sig.bin"
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#define LSFM_DISABLE_MASK_NONE (0x00000000) /*Disable all LS falcons*/
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#define LSFM_DISABLE_MASK_ALL (0xFFFFFFFF) /*Enable all LS falcons*/
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#define PMU_SECURE_MODE (0x1)
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#define PMU_LSFM_MANAGED (0x2)
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/*ACR load related*/
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/*!
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* Supporting maximum of 2 regions.
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* This is needed to pre-allocate space in DMEM
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*/
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#define T210_FLCN_ACR_MAX_REGIONS (2)
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#define LSF_BOOTSTRAP_OWNER_RESERVED_DMEM_SIZE (0x200)
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/*!
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* Falcon Id Defines
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* Defines a common Light Secure Falcon identifier.
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*/
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#define LSF_FALCON_ID_PMU (0)
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#define LSF_FALCON_ID_FECS (2)
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#define LSF_FALCON_ID_GPCCS (3)
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#define LSF_FALCON_ID_INVALID (0xFFFFFFFF)
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/*!
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* Bootstrap Owner Defines
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*/
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#define LSF_BOOTSTRAP_OWNER_DEFAULT (LSF_FALCON_ID_PMU)
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/*!
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* Image Status Defines
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*/
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#define LSF_IMAGE_STATUS_NONE (0)
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#define LSF_IMAGE_STATUS_COPY (1)
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#define LSF_IMAGE_STATUS_VALIDATION_CODE_FAILED (2)
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#define LSF_IMAGE_STATUS_VALIDATION_DATA_FAILED (3)
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#define LSF_IMAGE_STATUS_VALIDATION_DONE (4)
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#define LSF_IMAGE_STATUS_VALIDATION_SKIPPED (5)
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#define LSF_IMAGE_STATUS_BOOTSTRAP_READY (6)
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/*LSB header related defines*/
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#define NV_FLCN_ACR_LSF_FLAG_LOAD_CODE_AT_0_FALSE 0
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#define NV_FLCN_ACR_LSF_FLAG_LOAD_CODE_AT_0_TRUE 1
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#define NV_FLCN_ACR_LSF_FLAG_DMACTL_REQ_CTX_FALSE 0
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#define NV_FLCN_ACR_LSF_FLAG_DMACTL_REQ_CTX_TRUE 4
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/*!
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* Light Secure WPR Content Alignments
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*/
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#define LSF_LSB_HEADER_ALIGNMENT 256
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#define LSF_BL_DATA_ALIGNMENT 256
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#define LSF_BL_DATA_SIZE_ALIGNMENT 256
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#define LSF_BL_CODE_SIZE_ALIGNMENT 256
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/*!
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* Falcon UCODE header index.
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*/
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#define FLCN_NL_UCODE_HDR_OS_CODE_OFF_IND (0)
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#define FLCN_NL_UCODE_HDR_OS_CODE_SIZE_IND (1)
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#define FLCN_NL_UCODE_HDR_OS_DATA_OFF_IND (2)
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#define FLCN_NL_UCODE_HDR_OS_DATA_SIZE_IND (3)
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#define FLCN_NL_UCODE_HDR_NUM_APPS_IND (4)
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/*!
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* There are total N number of Apps with code and offset defined in UCODE header
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* This macro provides the CODE and DATA offset and size of Ath application.
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*/
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#define FLCN_NL_UCODE_HDR_APP_CODE_START_IND (5)
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#define FLCN_NL_UCODE_HDR_APP_CODE_OFF_IND(N, A) \
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(FLCN_NL_UCODE_HDR_APP_CODE_START_IND + (A*2))
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#define FLCN_NL_UCODE_HDR_APP_CODE_SIZE_IND(N, A) \
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(FLCN_NL_UCODE_HDR_APP_CODE_START_IND + (A*2) + 1)
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#define FLCN_NL_UCODE_HDR_APP_CODE_END_IND(N) \
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(FLCN_NL_UCODE_HDR_APP_CODE_START_IND + (N*2) - 1)
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#define FLCN_NL_UCODE_HDR_APP_DATA_START_IND(N) \
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(FLCN_NL_UCODE_HDR_APP_CODE_END_IND(N) + 1)
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#define FLCN_NL_UCODE_HDR_APP_DATA_OFF_IND(N, A) \
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(FLCN_NL_UCODE_HDR_APP_DATA_START_IND(N) + (A*2))
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#define FLCN_NL_UCODE_HDR_APP_DATA_SIZE_IND(N, A) \
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(FLCN_NL_UCODE_HDR_APP_DATA_START_IND(N) + (A*2) + 1)
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#define FLCN_NL_UCODE_HDR_APP_DATA_END_IND(N) \
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(FLCN_NL_UCODE_HDR_APP_DATA_START_IND(N) + (N*2) - 1)
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#define FLCN_NL_UCODE_HDR_OS_OVL_OFF_IND(N) \
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(FLCN_NL_UCODE_HDR_APP_DATA_END_IND(N) + 1)
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#define FLCN_NL_UCODE_HDR_OS_OVL_SIZE_IND(N) \
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(FLCN_NL_UCODE_HDR_APP_DATA_END_IND(N) + 2)
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/*Externs*/
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/*Structs*/
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/*!
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* Light Secure Falcon Ucode Description Defines
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* This stucture is prelim and may change as the ucode signing flow evolves.
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*/
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struct lsf_ucode_desc {
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u8 prd_keys[2][16];
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u8 dbg_keys[2][16];
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u32 b_prd_present;
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u32 b_dbg_present;
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u32 falcon_id;
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};
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/*!
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* Light Secure WPR Header
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* Defines state allowing Light Secure Falcon bootstrapping.
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*
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* falcon_id - LS falcon ID
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* lsb_offset - Offset into WPR region holding LSB header
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* bootstrap_owner - Bootstrap OWNER (either PMU or SEC2)
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* lazy_bootstrap - Skip bootstrapping by ACR
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* status - Bootstrapping status
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*/
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struct lsf_wpr_header {
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u32 falcon_id;
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u32 lsb_offset;
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u32 bootstrap_owner;
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u32 lazy_bootstrap;
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u32 status;
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};
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struct lsf_lsb_header {
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struct lsf_ucode_desc signature;
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u32 ucode_off;
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u32 ucode_size;
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u32 data_size;
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u32 bl_code_size;
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u32 bl_imem_off;
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u32 bl_data_off;
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u32 bl_data_size;
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u32 app_code_off;
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u32 app_code_size;
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u32 app_data_off;
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u32 app_data_size;
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u32 flags;
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};
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/*!
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* Structure used by the boot-loader to load the rest of the code. This has
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* to be filled by host and copied into DMEM at offset provided in the
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* hsflcn_bl_desc.bl_desc_dmem_load_off.
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*
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* signature - 16B signature for secure code. 0s if no secure code
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* ctx_dma - CtxDma to be used by BL while loading code/data
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* code_dma_base - 256B aligned Physical FB Address where code is located
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* non_sec_code_off - Offset from code_dma_base where the nonSecure code is
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* located. The offset must be multiple of 256 to help perf
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* non_sec_code_size - The size of the nonSecure code part.
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* sec_code_size - Offset from code_dma_base where the secure code is
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* located. The offset must be multiple of 256 to help perf
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* code_entry_point - Code entry point which will be invoked by BL after
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* code is loaded.
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* data_dma_base - 256B aligned Physical FB Address where data is located.
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* data_size - Size of data block. Should be multiple of 256B
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*/
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struct flcn_bl_dmem_desc {
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u32 reserved[4]; /*Should be the first element..*/
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u32 signature[4]; /*Should be the first element..*/
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u32 ctx_dma;
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u32 code_dma_base;
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u32 non_sec_code_off;
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u32 non_sec_code_size;
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u32 sec_code_off;
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u32 sec_code_size;
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u32 code_entry_point;
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u32 data_dma_base;
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u32 data_size;
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};
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/*!
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* Legacy structure used by the current PMU/DPU bootloader.
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*/
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struct loader_config {
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u32 dma_idx;
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u32 code_dma_base; /*<! upper 32-bits of 40-bit dma address*/
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u32 code_size_total;
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u32 code_size_to_load;
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u32 code_entry_point;
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u32 data_dma_base; /*<! upper 32-bits of 40-bit dma address*/
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u32 data_size; /*<! initialized data of the application */
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u32 overlay_dma_base; /*<! upper 32-bits of the 40-bit dma address*/
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u32 argc;
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u32 argv;
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};
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/*!
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* Union of all supported structures used by bootloaders.
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*/
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union flcn_bl_generic_desc {
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struct flcn_bl_dmem_desc bl_dmem_desc;
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struct loader_config loader_cfg;
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};
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struct flcn_ucode_img {
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u32 *header; /*only some falcons have header*/
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u32 *data;
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struct pmu_ucode_desc *desc; /*only some falcons have descriptor*/
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u32 data_size;
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void *fw_ver; /*NV2080_CTRL_GPU_GET_FIRMWARE_VERSION_PARAMS struct*/
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u8 load_entire_os_data; /* load the whole osData section at boot time.*/
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struct lsf_ucode_desc *lsf_desc; /* NULL if not a light secure falcon.*/
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u8 free_res_allocs;/*True if there a resources to freed by the client.*/
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u32 flcn_inst;
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};
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/*!
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* LSFM Managed Ucode Image
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* next : Next image the list, NULL if last.
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* wpr_header : WPR header for this ucode image
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* lsb_header : LSB header for this ucode image
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* bl_gen_desc : Bootloader generic desc structure for this ucode image
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* bl_gen_desc_size : Sizeof bootloader desc structure for this ucode image
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* full_ucode_size : Surface size required for final ucode image
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* ucode_img : Ucode image info
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*/
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struct lsfm_managed_ucode_img {
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struct lsfm_managed_ucode_img *next;
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struct lsf_wpr_header wpr_header;
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struct lsf_lsb_header lsb_header;
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union flcn_bl_generic_desc bl_gen_desc;
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u32 bl_gen_desc_size;
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u32 full_ucode_size;
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struct flcn_ucode_img ucode_img;
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};
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struct ls_flcn_mgr {
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u16 managed_flcn_cnt;
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u32 wpr_size;
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u32 disable_mask;
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struct lsfm_managed_ucode_img *ucode_img_list;
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void *wpr_client_req_state;/*PACR_CLIENT_REQUEST_STATE originally*/
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};
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/*ACR related structs*/
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/*!
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* start_addr - Starting address of region
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* end_addr - Ending address of region
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* region_id - Region ID
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* read_mask - Read Mask
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* write_mask - WriteMask
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* client_mask - Bit map of all clients currently using this region
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*/
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struct flcn_acr_region_prop {
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u32 start_addr;
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u32 end_addr;
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u32 region_id;
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u32 read_mask;
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u32 write_mask;
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u32 client_mask;
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};
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/*!
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* no_regions - Number of regions used.
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* region_props - Region properties
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*/
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struct flcn_acr_regions {
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u32 no_regions;
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struct flcn_acr_region_prop region_props[T210_FLCN_ACR_MAX_REGIONS];
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};
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/*!
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* reserved_dmem-When the bootstrap owner has done bootstrapping other falcons,
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* and need to switch into LS mode, it needs to have its own
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* actual DMEM image copied into DMEM as part of LS setup. If
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* ACR desc is at location 0, it will definitely get overwritten
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* causing data corruption. Hence we are reserving 0x200 bytes
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* to give room for any loading data. NOTE: This has to be the
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* first member always
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* signature - Signature of ACR ucode.
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* wpr_region_id - Region ID holding the WPR header and its details
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* wpr_offset - Offset from the WPR region holding the wpr header
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* regions - Region descriptors
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* nonwpr_ucode_blob_start -stores non-WPR start where kernel stores ucode blob
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* nonwpr_ucode_blob_end -stores non-WPR end where kernel stores ucode blob
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*/
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struct flcn_acr_desc {
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union {
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u32 reserved_dmem[(LSF_BOOTSTRAP_OWNER_RESERVED_DMEM_SIZE/4)];
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u32 signatures[4];
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} ucode_reserved_space;
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/*Always 1st*/
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u32 wpr_region_id;
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u32 wpr_offset;
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u32 mmu_mem_range;
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struct flcn_acr_regions regions;
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u32 nonwpr_ucode_blob_size;
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u64 nonwpr_ucode_blob_start;
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};
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/*!
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* The header used by RM to figure out code and data sections of bootloader.
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*
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* bl_code_off - Offset of code section in the image
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* bl_code_size - Size of code section in the image
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* bl_data_off - Offset of data section in the image
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* bl_data_size - Size of data section in the image
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*/
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struct hsflcn_bl_img_hdr {
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u32 bl_code_off;
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u32 bl_code_size;
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u32 bl_data_off;
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u32 bl_data_size;
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};
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/*!
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* The descriptor used by RM to figure out the requirements of boot loader.
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*
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* bl_start_tag - Starting tag of bootloader
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* bl_desc_dmem_load_off - Dmem offset where _def_rm_flcn_bl_dmem_desc
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to be loaded
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* bl_img_hdr - Description of the image
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*/
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struct hsflcn_bl_desc {
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u32 bl_start_tag;
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u32 bl_desc_dmem_load_off;
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struct hsflcn_bl_img_hdr bl_img_hdr;
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};
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struct bin_hdr {
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u32 bin_magic; /* 0x10de */
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u32 bin_ver; /* versioning of bin format */
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u32 bin_size; /* entire image size including this header */
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u32 header_offset; /* Header offset of executable binary metadata,
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start @ offset- 0x100 */
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u32 data_offset; /* Start of executable binary data, start @
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offset- 0x200 */
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u32 data_size; /* Size ofexecutable binary */
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};
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struct acr_fw_header {
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u32 sig_dbg_offset;
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u32 sig_dbg_size;
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u32 sig_prod_offset;
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u32 sig_prod_size;
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u32 patch_loc;
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u32 patch_sig;
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u32 hdr_offset; /*this header points to acr_ucode_header_t210_load*/
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u32 hdr_size; /*size of above header*/
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};
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struct acr_gm20b {
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u64 ucode_blob_start;
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u32 ucode_blob_size;
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struct bin_hdr *bl_bin_hdr;
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struct hsflcn_bl_desc *pmu_hsbl_desc;
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struct bin_hdr *hsbin_hdr;
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struct acr_fw_header *fw_hdr;
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u32 pmu_args;
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const struct firmware *acr_fw;
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struct pmu_mem_desc acr_ucode;
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const struct firmware *hsbl_fw;
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struct pmu_mem_desc hsbl_ucode;
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struct flcn_bl_dmem_desc bl_dmem_desc;
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const struct firmware *pmu_fw;
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const struct firmware *pmu_desc;
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};
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void gm20b_init_secure_pmu(struct gpu_ops *gops);
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int prepare_ucode_blob(struct gk20a *g);
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int pmu_ucode_details(struct gk20a *g, struct flcn_ucode_img *p_img);
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int fecs_ucode_details(struct gk20a *g, struct flcn_ucode_img *p_img);
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int gpccs_ucode_details(struct gk20a *g, struct flcn_ucode_img *p_img);
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int gm20b_bootstrap_hs_flcn(struct gk20a *g);
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int gm20b_pmu_setup_sw(struct gk20a *g);
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int pmu_exec_gen_bl(struct gk20a *g, void *desc, u8 b_wait_for_halt);
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int pmu_wait_for_halt(struct gk20a *g, unsigned int timeout_us);
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int clear_halt_interrupt_status(struct gk20a *g, unsigned int timeout);
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#endif /*__ACR_GM20B_H_*/
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