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- Enable the reporting of PRI access violation. - While enabling PRI access violation, it has been found that PRI timeout reporting was added part of ptimer. Since both PRI timeout and access violation are logically co-related, we have decided to add them as part of PRIV_RING. Jira NVGPU-3087 Change-Id: I5543f1b5d0ab01354ffff16c172a635b2df1fd26 Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2087824 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
127 lines
3.8 KiB
C
127 lines
3.8 KiB
C
/*
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* Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/log.h>
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#include <nvgpu/io.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/nvgpu_err.h>
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#include "ptimer_gk20a.h"
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#include <nvgpu/hw/gk20a/hw_timer_gk20a.h>
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void gk20a_ptimer_isr(struct gk20a *g)
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{
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u32 save0, save1, fecs_errcode = 0;
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int ret = 0;
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u32 inst = 0U;
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u32 error_addr;
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save0 = gk20a_readl(g, timer_pri_timeout_save_0_r());
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if (timer_pri_timeout_save_0_fecs_tgt_v(save0) != 0U) {
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/*
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* write & addr fields in timeout_save0
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* might not be reliable
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*/
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fecs_errcode = gk20a_readl(g,
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timer_pri_timeout_fecs_errcode_r());
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}
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save1 = gk20a_readl(g, timer_pri_timeout_save_1_r());
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error_addr = timer_pri_timeout_save_0_addr_v(save0) << 2;
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nvgpu_err(g, "PRI timeout: ADR 0x%08x "
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"%s DATA 0x%08x",
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error_addr,
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(timer_pri_timeout_save_0_write_v(save0) != 0U) ?
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"WRITE" : "READ", save1);
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gk20a_writel(g, timer_pri_timeout_save_0_r(), 0);
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gk20a_writel(g, timer_pri_timeout_save_1_r(), 0);
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if (fecs_errcode != 0U) {
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nvgpu_err(g, "FECS_ERRCODE 0x%08x", fecs_errcode);
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if (g->ops.priv_ring.decode_error_code != NULL) {
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g->ops.priv_ring.decode_error_code(g,
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fecs_errcode);
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}
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/* FECS was the target of PRI access */
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inst = 1U;
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/* SAVE_0_ADDR cannot be used in this case */
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error_addr = 0U;
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}
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if (g->ops.priv_ring.err_ops.report_timeout_err != NULL) {
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ret = g->ops.priv_ring.err_ops.report_timeout_err(g,
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NVGPU_ERR_MODULE_PRI,
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inst,
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GPU_PRI_TIMEOUT_ERROR,
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error_addr,
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fecs_errcode);
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if (ret != 0) {
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nvgpu_err(g, "Failed to report PRI Timout error: "
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"inst=%u, err_addr=%u, err_code=%u",
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inst, error_addr, fecs_errcode);
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}
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}
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}
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int gk20a_read_ptimer(struct gk20a *g, u64 *value)
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{
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const unsigned int max_iterations = 3;
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unsigned int i = 0;
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u32 gpu_timestamp_hi_prev = 0;
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if (value == NULL) {
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return -EINVAL;
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}
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/* Note. The GPU nanosecond timer consists of two 32-bit
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* registers (high & low). To detect a possible low register
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* wrap-around between the reads, we need to read the high
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* register before and after low. The wraparound happens
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* approximately once per 4 secs. */
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/* get initial gpu_timestamp_hi value */
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gpu_timestamp_hi_prev = gk20a_readl(g, timer_time_1_r());
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for (i = 0; i < max_iterations; ++i) {
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u32 gpu_timestamp_hi = 0;
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u32 gpu_timestamp_lo = 0;
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gpu_timestamp_lo = gk20a_readl(g, timer_time_0_r());
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gpu_timestamp_hi = gk20a_readl(g, timer_time_1_r());
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if (gpu_timestamp_hi == gpu_timestamp_hi_prev) {
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*value = (((u64)gpu_timestamp_hi) << 32) |
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gpu_timestamp_lo;
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return 0;
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}
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/* wrap-around detected, retry */
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gpu_timestamp_hi_prev = gpu_timestamp_hi;
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}
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/* too many iterations, bail out */
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nvgpu_err(g, "failed to read ptimer");
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return -EBUSY;
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}
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