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b4ec1c5dff
Renamed and moved from fifo to channel gk20a_debug_dump_all_channel_status_ramfc -> nvgpu_channel_debug_dump_all gk20a_dump_channel_status_ramfc -> gk20a_channel_debug_dump gv11b_dump_channel_status_ramfc -> gv11b_channel_debug_dump Moved nvgpu_channel_dump_info struct to channel.h Moved nvgpu_channel_hw_state struct to channel.h Moved dump_channel_status_ramfc fifo ops to channel ops as debug_dump JIRA NVGPU-2978 Change-Id: I696e5029d9e6ca4dc3516651b4d4f5230fe8b0b0 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2092709 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
59 lines
2.4 KiB
C
59 lines
2.4 KiB
C
/*
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* Copyright (c) 2014-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_PBDMA_GM20B_H
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#define NVGPU_PBDMA_GM20B_H
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#include <nvgpu/types.h>
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struct gk20a;
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struct gk20a_debug_output;
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struct nvgpu_channel_dump_info;
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void gm20b_pbdma_intr_enable(struct gk20a *g, bool enable);
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bool gm20b_pbdma_handle_intr_0(struct gk20a *g, u32 pbdma_id,
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u32 pbdma_intr_0, u32 *error_notifier);
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bool gm20b_pbdma_handle_intr_1(struct gk20a *g, u32 pbdma_id,
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u32 pbdma_intr_1, u32 *error_notifier);
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bool gm20b_pbdma_handle_intr(struct gk20a *g, u32 pbdma_id,
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u32 *error_notifier);
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u32 gm20b_pbdma_get_signature(struct gk20a *g);
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u32 gm20b_pbdma_read_data(struct gk20a *g, u32 pbdma_id);
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void gm20b_pbdma_reset_header(struct gk20a *g, u32 pbdma_id);
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void gm20b_pbdma_reset_method(struct gk20a *g, u32 pbdma_id,
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u32 pbdma_method_index);
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u32 gm20b_pbdma_acquire_val(u64 timeout);
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void gm20b_pbdma_dump_status(struct gk20a *g, struct gk20a_debug_output *o);
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u32 gm20b_pbdma_device_fatal_0_intr_descs(void);
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u32 gm20b_pbdma_channel_fatal_0_intr_descs(void);
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u32 gm20b_pbdma_restartable_0_intr_descs(void);
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void gm20b_pbdma_clear_all_intr(struct gk20a *g, u32 pbdma_id);
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void gm20b_pbdma_disable_and_clear_all_intr(struct gk20a *g);
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void gm20b_pbdma_syncpoint_debug_dump(struct gk20a *g,
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struct gk20a_debug_output *o,
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struct nvgpu_channel_dump_info *info);
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#endif /* NVGPU_PBDMA_GM20B_H */
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