mirror of
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9812bd5eea
On Maxwell comptaglines are assigned per 128k, but preferred big page size for graphics is 64k. Bit 16 of GPU VA is used for determining which half of comptagline is used. This creates problems if user space wants to map a page multiple times and to arbitrary GPU VA. In one mapping the page might be mapped to lower half of 128k comptagline, and in another mapping the page might be mapped to upper half. Turn on mode where MSB of comptagline in PTE is used instead of bit 16 for determining the comptagline lower/upper half selection. Bug 1704834 Change-Id: If87e8f6ac0fc9c5624e80fa1ba2ceeb02781355b Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/924322 Reviewed-by: Alex Waterman <alexw@nvidia.com>
322 lines
7.3 KiB
C
322 lines
7.3 KiB
C
/*
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* Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/*
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* Function naming determines intended use:
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*
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* <x>_r(void) : Returns the offset for register <x>.
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*
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* <x>_o(void) : Returns the offset for element <x>.
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*
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* <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
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*
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* <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
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*
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* <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
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* and masked to place it at field <y> of register <x>. This value
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* can be |'d with others to produce a full register value for
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* register <x>.
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*
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* <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
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* value can be ~'d and then &'d to clear the value of field <y> for
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* register <x>.
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*
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* <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
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* to place it at field <y> of register <x>. This value can be |'d
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* with others to produce a full register value for <x>.
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*
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* <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
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* <x> value 'r' after being shifted to place its LSB at bit 0.
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* This value is suitable for direct comparison with other unshifted
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* values appropriate for use in field <y> of register <x>.
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*
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* <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
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* field <y> of register <x>. This value is suitable for direct
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* comparison with unshifted values appropriate for use in field <y>
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* of register <x>.
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*/
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#ifndef _hw_fb_gm20b_h_
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#define _hw_fb_gm20b_h_
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static inline u32 fb_fbhub_num_active_ltcs_r(void)
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{
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return 0x00100800;
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}
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static inline u32 fb_mmu_ctrl_r(void)
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{
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return 0x00100c80;
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}
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static inline u32 fb_mmu_ctrl_vm_pg_size_f(u32 v)
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{
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return (v & 0x1) << 0;
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}
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static inline u32 fb_mmu_ctrl_vm_pg_size_128kb_f(void)
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{
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return 0x0;
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}
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static inline u32 fb_mmu_ctrl_vm_pg_size_64kb_f(void)
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{
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return 0x1;
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}
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static inline u32 fb_mmu_ctrl_pri_fifo_empty_v(u32 r)
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{
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return (r >> 15) & 0x1;
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}
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static inline u32 fb_mmu_ctrl_pri_fifo_empty_false_f(void)
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{
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return 0x0;
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}
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static inline u32 fb_mmu_ctrl_pri_fifo_space_v(u32 r)
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{
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return (r >> 16) & 0xff;
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}
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static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_v(u32 r)
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{
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return (r >> 11) & 0x1;
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}
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static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_true_f(void)
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{
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return 0x800;
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}
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static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_false_f(void)
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{
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return 0x0;
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}
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static inline u32 fb_mmu_ctrl_use_full_comp_tag_line_v(u32 r)
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{
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return (r >> 12) & 0x1;
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}
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static inline u32 fb_mmu_ctrl_use_full_comp_tag_line_true_f(void)
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{
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return 0x1000;
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}
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static inline u32 fb_priv_mmu_phy_secure_r(void)
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{
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return 0x00100ce4;
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}
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static inline u32 fb_mmu_invalidate_pdb_r(void)
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{
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return 0x00100cb8;
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}
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static inline u32 fb_mmu_invalidate_pdb_aperture_vid_mem_f(void)
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{
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return 0x0;
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}
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static inline u32 fb_mmu_invalidate_pdb_addr_f(u32 v)
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{
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return (v & 0xfffffff) << 4;
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}
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static inline u32 fb_mmu_invalidate_r(void)
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{
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return 0x00100cbc;
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}
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static inline u32 fb_mmu_invalidate_all_va_true_f(void)
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{
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return 0x1;
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}
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static inline u32 fb_mmu_invalidate_all_pdb_true_f(void)
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{
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return 0x2;
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}
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static inline u32 fb_mmu_invalidate_trigger_s(void)
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{
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return 1;
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}
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static inline u32 fb_mmu_invalidate_trigger_f(u32 v)
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{
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return (v & 0x1) << 31;
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}
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static inline u32 fb_mmu_invalidate_trigger_m(void)
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{
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return 0x1 << 31;
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}
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static inline u32 fb_mmu_invalidate_trigger_v(u32 r)
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{
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return (r >> 31) & 0x1;
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}
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static inline u32 fb_mmu_invalidate_trigger_true_f(void)
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{
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return 0x80000000;
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}
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static inline u32 fb_mmu_debug_wr_r(void)
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{
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return 0x00100cc8;
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}
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static inline u32 fb_mmu_debug_wr_aperture_s(void)
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{
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return 2;
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}
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static inline u32 fb_mmu_debug_wr_aperture_f(u32 v)
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{
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return (v & 0x3) << 0;
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}
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static inline u32 fb_mmu_debug_wr_aperture_m(void)
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{
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return 0x3 << 0;
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}
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static inline u32 fb_mmu_debug_wr_aperture_v(u32 r)
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{
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return (r >> 0) & 0x3;
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}
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static inline u32 fb_mmu_debug_wr_aperture_vid_mem_f(void)
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{
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return 0x0;
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}
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static inline u32 fb_mmu_debug_wr_vol_false_f(void)
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{
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return 0x0;
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}
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static inline u32 fb_mmu_debug_wr_vol_true_v(void)
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{
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return 0x00000001;
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}
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static inline u32 fb_mmu_debug_wr_vol_true_f(void)
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{
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return 0x4;
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}
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static inline u32 fb_mmu_debug_wr_addr_f(u32 v)
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{
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return (v & 0xfffffff) << 4;
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}
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static inline u32 fb_mmu_debug_wr_addr_alignment_v(void)
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{
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return 0x0000000c;
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}
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static inline u32 fb_mmu_debug_rd_r(void)
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{
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return 0x00100ccc;
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}
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static inline u32 fb_mmu_debug_rd_aperture_vid_mem_f(void)
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{
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return 0x0;
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}
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static inline u32 fb_mmu_debug_rd_vol_false_f(void)
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{
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return 0x0;
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}
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static inline u32 fb_mmu_debug_rd_addr_f(u32 v)
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{
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return (v & 0xfffffff) << 4;
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}
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static inline u32 fb_mmu_debug_rd_addr_alignment_v(void)
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{
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return 0x0000000c;
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}
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static inline u32 fb_mmu_debug_ctrl_r(void)
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{
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return 0x00100cc4;
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}
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static inline u32 fb_mmu_debug_ctrl_debug_v(u32 r)
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{
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return (r >> 16) & 0x1;
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}
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static inline u32 fb_mmu_debug_ctrl_debug_m(void)
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{
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return 0x1 << 16;
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}
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static inline u32 fb_mmu_debug_ctrl_debug_enabled_v(void)
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{
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return 0x00000001;
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}
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static inline u32 fb_mmu_debug_ctrl_debug_enabled_f(void)
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{
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return 0x10000;
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}
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static inline u32 fb_mmu_debug_ctrl_debug_disabled_v(void)
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{
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return 0x00000000;
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}
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static inline u32 fb_mmu_debug_ctrl_debug_disabled_f(void)
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{
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return 0x0;
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}
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static inline u32 fb_mmu_vpr_info_r(void)
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{
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return 0x00100cd0;
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}
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static inline u32 fb_mmu_vpr_info_index_f(u32 v)
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{
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return (v & 0x3) << 0;
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}
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static inline u32 fb_mmu_vpr_info_index_v(u32 r)
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{
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return (r >> 0) & 0x3;
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}
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static inline u32 fb_mmu_vpr_info_index_addr_lo_v(void)
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{
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return 0x00000000;
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}
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static inline u32 fb_mmu_vpr_info_index_addr_hi_v(void)
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{
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return 0x00000001;
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}
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static inline u32 fb_mmu_vpr_info_index_cya_lo_v(void)
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{
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return 0x00000002;
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}
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static inline u32 fb_mmu_vpr_info_index_cya_hi_v(void)
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{
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return 0x00000003;
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}
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static inline u32 fb_mmu_vpr_info_fetch_f(u32 v)
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{
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return (v & 0x1) << 2;
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}
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static inline u32 fb_mmu_vpr_info_fetch_v(u32 r)
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{
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return (r >> 2) & 0x1;
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}
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static inline u32 fb_mmu_vpr_info_fetch_false_v(void)
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{
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return 0x00000000;
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}
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static inline u32 fb_mmu_vpr_info_fetch_true_v(void)
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{
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return 0x00000001;
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}
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static inline u32 fb_mmu_wpr_info_r(void)
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{
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return 0x00100cd4;
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}
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static inline u32 fb_mmu_wpr_info_index_f(u32 v)
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{
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return (v & 0xf) << 0;
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}
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static inline u32 fb_mmu_wpr_info_index_allow_read_v(void)
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{
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return 0x00000000;
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}
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static inline u32 fb_mmu_wpr_info_index_allow_write_v(void)
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{
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return 0x00000001;
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}
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static inline u32 fb_mmu_wpr_info_index_wpr1_addr_lo_v(void)
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{
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return 0x00000002;
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}
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static inline u32 fb_mmu_wpr_info_index_wpr1_addr_hi_v(void)
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{
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return 0x00000003;
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}
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static inline u32 fb_mmu_wpr_info_index_wpr2_addr_lo_v(void)
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{
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return 0x00000004;
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}
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static inline u32 fb_mmu_wpr_info_index_wpr2_addr_hi_v(void)
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{
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return 0x00000005;
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}
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#endif
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