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6fe9bb835b
struct nvgpu_channel_sync is moved to a private header i.e. channel_sync_priv.h present in common/sync/. All accesses to callback functions inside the struct nvgpu_channel_sync in NVGPU driver is replaced by the public channel_sync specific APIs. Jira NVGPU-1093 Change-Id: I52d57b3d458993203a3ac6b160fb569effbe5a66 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1929783 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
119 lines
3.5 KiB
C
119 lines
3.5 KiB
C
/*
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* GK20A Channel Synchronization Abstraction
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*
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* Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/kmem.h>
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#include <nvgpu/log.h>
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#include <nvgpu/atomic.h>
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#include <nvgpu/bug.h>
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#include <nvgpu/list.h>
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#include <nvgpu/nvhost.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/os_fence.h>
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#include <nvgpu/os_fence_syncpts.h>
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#include <nvgpu/os_fence_semas.h>
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#include <nvgpu/channel.h>
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#include <nvgpu/channel_sync.h>
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#include <nvgpu/channel_sync_syncpt.h>
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#include <nvgpu/channel_sync_semaphore.h>
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#include "channel_sync_priv.h"
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#include "gk20a/fence_gk20a.h"
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#include "gk20a/mm_gk20a.h"
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struct nvgpu_channel_sync *nvgpu_channel_sync_create(struct channel_gk20a *c,
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bool user_managed)
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{
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if (nvgpu_has_syncpoints(c->g)) {
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return nvgpu_channel_sync_syncpt_create(c, user_managed);
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} else {
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return nvgpu_channel_sync_semaphore_create(c, user_managed);
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}
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}
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bool nvgpu_channel_sync_needs_os_fence_framework(struct gk20a *g)
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{
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return !nvgpu_has_syncpoints(g);
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}
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bool nvgpu_has_syncpoints(struct gk20a *g)
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{
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#ifdef CONFIG_TEGRA_GK20A_NVHOST
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return nvgpu_is_enabled(g, NVGPU_HAS_SYNCPOINTS) &&
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!g->disable_syncpoints;
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#else
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return false;
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#endif
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}
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int nvgpu_channel_sync_wait_fence_fd(struct nvgpu_channel_sync *s, int fd,
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struct priv_cmd_entry *entry, u32 max_wait_cmds)
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{
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return s->wait_fence_fd(s, fd, entry, max_wait_cmds);
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}
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int nvgpu_channel_sync_incr(struct nvgpu_channel_sync *s,
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struct priv_cmd_entry *entry, struct gk20a_fence *fence,
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bool need_sync_fence, bool register_irq)
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{
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return s->incr(s, entry, fence, need_sync_fence, register_irq);
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}
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int nvgpu_channel_sync_incr_user(struct nvgpu_channel_sync *s,
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int wait_fence_fd, struct priv_cmd_entry *entry,
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struct gk20a_fence *fence, bool wfi, bool need_sync_fence,
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bool register_irq)
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{
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return s->incr_user(s, wait_fence_fd, entry, fence, wfi,
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need_sync_fence, register_irq);
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}
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void nvgpu_channel_sync_set_min_eq_max(struct nvgpu_channel_sync *s)
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{
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s->set_min_eq_max(s);
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}
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void nvgpu_channel_sync_set_safe_state(struct nvgpu_channel_sync *s)
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{
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s->set_safe_state(s);
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}
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void nvgpu_channel_sync_destroy(struct nvgpu_channel_sync *sync,
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bool set_safe_state)
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{
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if (set_safe_state) {
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sync->set_safe_state(sync);
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}
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sync->destroy(sync);
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}
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void nvgpu_channel_sync_get_ref(struct nvgpu_channel_sync *s)
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{
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nvgpu_atomic_inc(&s->refcount);
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}
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bool nvgpu_channel_sync_put_ref_and_check(struct nvgpu_channel_sync *s)
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{
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return nvgpu_atomic_dec_and_test(&s->refcount);
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}
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