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251e3eaa80
Support following changes related to platform atomic feature NV_PFB_PRI_MMU_CTRL_ATOMIC_CAPABILITY_MODE to RMW MODE NV_PFB_PRI_MMU_CTRL_ATOMIC_CAPABILITY_SYS_NCOH_MODE to L2 NV_PFB_HSHUB_NUM_ACTIVE_LTCS_HUB_SYS_ATOMIC_MODE to USE_RMW NV_PFB_FBHUB_NUM_ACTIVE_LTCS_HUB_SYS_ATOMIC_MODE to USE_RMW NV_PFB_FBHUB_NUM_ACTIVE_LTCS_HUB_SYS_NCOH_ATOMIC_MODE to USE_READ In gv11b, FBHUB_NUM_ACTIVE_LTCS register has read only privilege, so atomic mode register bits cannot be updated from kernel code. atomic capability and atomic_sys_ncoh_mode bits are copied from fb mmu_ctrl to gpcs_mmu_ctrl register. new tu104 hal for fb_enable_nvlink function. Change-Id: Ia78986c1c56795c6efad20f4ba42700ef1c2c1ad Signed-off-by: Vinod G <vinodg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2013481 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
65 lines
2.6 KiB
C
65 lines
2.6 KiB
C
/*
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* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_FB_TU104_H
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#define NVGPU_FB_TU104_H
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#include <nvgpu/types.h>
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struct gk20a;
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struct gr_gk20a;
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struct nvgpu_mem;
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void tu104_fb_enable_hub_intr(struct gk20a *g);
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void tu104_fb_disable_hub_intr(struct gk20a *g);
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bool tu104_fb_mmu_fault_pending(struct gk20a *g);
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void tu104_fb_hub_isr(struct gk20a *g);
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void fb_tu104_write_mmu_fault_buffer_lo_hi(struct gk20a *g, u32 index,
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u32 addr_lo, u32 addr_hi);
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u32 fb_tu104_read_mmu_fault_buffer_get(struct gk20a *g, u32 index);
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void fb_tu104_write_mmu_fault_buffer_get(struct gk20a *g, u32 index,
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u32 reg_val);
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u32 fb_tu104_read_mmu_fault_buffer_put(struct gk20a *g, u32 index);
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u32 fb_tu104_read_mmu_fault_buffer_size(struct gk20a *g, u32 index);
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void fb_tu104_write_mmu_fault_buffer_size(struct gk20a *g, u32 index,
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u32 reg_val);
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void fb_tu104_read_mmu_fault_addr_lo_hi(struct gk20a *g,
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u32 *addr_lo, u32 *addr_hi);
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void fb_tu104_read_mmu_fault_inst_lo_hi(struct gk20a *g,
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u32 *inst_lo, u32 *inst_hi);
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u32 fb_tu104_read_mmu_fault_info(struct gk20a *g);
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u32 fb_tu104_read_mmu_fault_status(struct gk20a *g);
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void fb_tu104_write_mmu_fault_status(struct gk20a *g, u32 reg_val);
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int fb_tu104_tlb_invalidate(struct gk20a *g, struct nvgpu_mem *pdb);
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int fb_tu104_mmu_invalidate_replay(struct gk20a *g,
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u32 invalidate_replay_val);
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void fb_tu104_init_cbc(struct gk20a *g, struct gr_gk20a *gr);
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int tu104_fb_apply_pdb_cache_war(struct gk20a *g);
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size_t tu104_fb_get_vidmem_size(struct gk20a *g);
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int tu104_fb_enable_nvlink(struct gk20a *g);
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#endif /* NVGPU_FB_TU104_H */
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