mirror of
git://nv-tegra.nvidia.com/linux-nvgpu.git
synced 2025-12-23 09:57:08 +03:00
d8c5ce3c85
Create a new directory fifo under common vgpu path moving all vgp common fifo files under that directory. Move vgpu runlist implementations to a new file runlist_vgpu.c and create corresponding header file. Also fix lines over 80 chars in fifo_vgpu.c Jira GVSCI-334 Change-Id: Ic00535b22a6066a0d27435b9a987de7fa701ea05 Signed-off-by: Aparna Das <aparnad@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2011762 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
60 lines
2.7 KiB
C
60 lines
2.7 KiB
C
/*
|
|
* Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved.
|
|
*
|
|
* Permission is hereby granted, free of charge, to any person obtaining a
|
|
* copy of this software and associated documentation files (the "Software"),
|
|
* to deal in the Software without restriction, including without limitation
|
|
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
|
* and/or sell copies of the Software, and to permit persons to whom the
|
|
* Software is furnished to do so, subject to the following conditions:
|
|
*
|
|
* The above copyright notice and this permission notice shall be included in
|
|
* all copies or substantial portions of the Software.
|
|
*
|
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
|
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
|
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
|
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
|
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
|
* DEALINGS IN THE SOFTWARE.
|
|
*/
|
|
|
|
#ifndef NVGPU_FIFO_VGPU_H
|
|
#define NVGPU_FIFO_VGPU_H
|
|
|
|
#include <nvgpu/types.h>
|
|
|
|
struct gk20a;
|
|
struct channel_gk20a;
|
|
struct fifo_gk20a;
|
|
struct tsg_gk20a;
|
|
|
|
int vgpu_init_fifo_setup_hw(struct gk20a *g);
|
|
void vgpu_channel_bind(struct channel_gk20a *ch);
|
|
void vgpu_channel_unbind(struct channel_gk20a *ch);
|
|
int vgpu_channel_alloc_inst(struct gk20a *g, struct channel_gk20a *ch);
|
|
void vgpu_channel_free_inst(struct gk20a *g, struct channel_gk20a *ch);
|
|
void vgpu_channel_enable(struct channel_gk20a *ch);
|
|
void vgpu_channel_disable(struct channel_gk20a *ch);
|
|
int vgpu_channel_setup_ramfc(struct channel_gk20a *ch, u64 gpfifo_base,
|
|
u32 gpfifo_entries,
|
|
unsigned long acquire_timeout, u32 flags);
|
|
int vgpu_fifo_init_engine_info(struct fifo_gk20a *f);
|
|
int vgpu_fifo_preempt_channel(struct gk20a *g, struct channel_gk20a *ch);
|
|
int vgpu_fifo_preempt_tsg(struct gk20a *g, struct tsg_gk20a *tsg);
|
|
int vgpu_fifo_wait_engine_idle(struct gk20a *g);
|
|
int vgpu_channel_set_timeslice(struct channel_gk20a *ch, u32 timeslice);
|
|
int vgpu_fifo_force_reset_ch(struct channel_gk20a *ch,
|
|
u32 err_code, bool verbose);
|
|
u32 vgpu_fifo_default_timeslice_us(struct gk20a *g);
|
|
int vgpu_tsg_open(struct tsg_gk20a *tsg);
|
|
void vgpu_tsg_release(struct tsg_gk20a *tsg);
|
|
int vgpu_tsg_bind_channel(struct tsg_gk20a *tsg,
|
|
struct channel_gk20a *ch);
|
|
int vgpu_tsg_unbind_channel(struct channel_gk20a *ch);
|
|
int vgpu_tsg_set_timeslice(struct tsg_gk20a *tsg, u32 timeslice);
|
|
int vgpu_enable_tsg(struct tsg_gk20a *tsg);
|
|
int vgpu_set_sm_exception_type_mask(struct channel_gk20a *ch, u32 mask);
|
|
#endif /* NVGPU_FIFO_VGPU_H */
|