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5c8f1619ce
All chips should use the waiting version of BAR1 bind since gm20b. Change gp10b and gp106 to do that. BAR1 is not used in Volta. JIRa NVGPU-588 Change-Id: Ib6957ebea4effa7c64f4d71522447fa6245728ed Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1730895 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
92 lines
2.8 KiB
C
92 lines
2.8 KiB
C
/*
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* Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/log.h>
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#include <nvgpu/soc.h>
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#include <nvgpu/mm.h>
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#include "gk20a/gk20a.h"
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#include "bus_gk20a.h"
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#include <nvgpu/hw/gk20a/hw_bus_gk20a.h>
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void gk20a_bus_init_hw(struct gk20a *g)
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{
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u32 intr_en_mask = 0;
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if (nvgpu_platform_is_silicon(g) || nvgpu_platform_is_fpga(g)) {
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intr_en_mask = bus_intr_en_0_pri_squash_m() |
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bus_intr_en_0_pri_fecserr_m() |
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bus_intr_en_0_pri_timeout_m();
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}
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gk20a_writel(g, bus_intr_en_0_r(), intr_en_mask);
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}
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void gk20a_bus_isr(struct gk20a *g)
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{
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u32 val;
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val = gk20a_readl(g, bus_intr_0_r());
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if (val & (bus_intr_0_pri_squash_m() |
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bus_intr_0_pri_fecserr_m() |
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bus_intr_0_pri_timeout_m())) {
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g->ops.ptimer.isr(g);
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} else {
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nvgpu_err(g, "Unhandled NV_PBUS_INTR_0: 0x%08x", val);
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}
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gk20a_writel(g, bus_intr_0_r(), val);
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}
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u32 gk20a_bus_set_bar0_window(struct gk20a *g, struct nvgpu_mem *mem,
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struct nvgpu_sgt *sgt, struct nvgpu_sgl *sgl, u32 w)
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{
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u64 bufbase = nvgpu_sgt_get_phys(g, sgt, sgl);
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u64 addr = bufbase + w * sizeof(u32);
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u32 hi = (u32)((addr & ~(u64)0xfffff)
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>> bus_bar0_window_target_bar0_window_base_shift_v());
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u32 lo = (u32)(addr & 0xfffff);
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u32 win = nvgpu_aperture_mask(g, mem,
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bus_bar0_window_target_sys_mem_noncoherent_f(),
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bus_bar0_window_target_sys_mem_coherent_f(),
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bus_bar0_window_target_vid_mem_f()) |
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bus_bar0_window_base_f(hi);
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nvgpu_log(g, gpu_dbg_mem,
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"0x%08x:%08x begin for %p,%p at [%llx,%llx] (sz %llx)",
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hi, lo, mem, sgl, bufbase,
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bufbase + nvgpu_sgt_get_phys(g, sgt, sgl),
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nvgpu_sgt_get_length(sgt, sgl));
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WARN_ON(!bufbase);
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if (g->mm.pramin_window != win) {
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gk20a_writel(g, bus_bar0_window_r(), win);
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gk20a_readl(g, bus_bar0_window_r());
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g->mm.pramin_window = win;
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}
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return lo;
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}
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