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git://nv-tegra.nvidia.com/linux-nvgpu.git
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d859c5f4a0
Moved gv11b_detect_ecc_enabled_units function from gv11b.c to gr_gv11b.c, as this is being used only in gr_gv11b file. In order to avoid GR code touching fuse registers, as it need to include fuse HW headers in GR code, introduced two fuse HALs which are being called from GR code. is_opt_ecc_enable for checking whether ecc enable bit is set in fuse register and is_opt_feature_overide_disable for checking whether feature override disable bit is set in fuse register. Initialized fuse HAL functions for chips that make use of those HAL functions. JIRA NVGPU-615 Change-Id: Iafe5a3940bb19cb3da51e270403450b63c2f67a3 Signed-off-by: Vinod G <vinodg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1775564 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
105 lines
3.3 KiB
C
105 lines
3.3 KiB
C
/*
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* GP10B FUSE
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*
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* Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/types.h>
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#include <nvgpu/fuse.h>
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#include <nvgpu/enabled.h>
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#include "gk20a/gk20a.h"
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#include "gm20b/fuse_gm20b.h"
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#include "fuse_gp10b.h"
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#include <nvgpu/hw/gp10b/hw_fuse_gp10b.h>
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int gp10b_fuse_check_priv_security(struct gk20a *g)
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{
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u32 gcplex_config;
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if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) {
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__nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false);
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__nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false);
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nvgpu_log(g, gpu_dbg_info, "priv sec is disabled in fmodel");
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return 0;
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}
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if (nvgpu_tegra_fuse_read_gcplex_config_fuse(g, &gcplex_config)) {
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nvgpu_err(g, "err reading gcplex config fuse, check fuse clk");
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return -EINVAL;
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}
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if (gk20a_readl(g, fuse_opt_priv_sec_en_r())) {
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/*
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* all falcons have to boot in LS mode and this needs
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* wpr_enabled set to 1 and vpr_auto_fetch_disable
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* set to 0. In this case gmmu tries to pull wpr
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* and vpr settings from tegra mc
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*/
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__nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true);
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__nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true);
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if ((gcplex_config &
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GCPLEX_CONFIG_WPR_ENABLED_MASK) &&
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!(gcplex_config &
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GCPLEX_CONFIG_VPR_AUTO_FETCH_DISABLE_MASK)) {
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if (gk20a_readl(g, fuse_opt_sec_debug_en_r()))
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nvgpu_log(g, gpu_dbg_info,
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"gcplex_config = 0x%08x, "
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"secure mode: ACR debug",
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gcplex_config);
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else
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nvgpu_log(g, gpu_dbg_info,
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"gcplex_config = 0x%08x, "
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"secure mode: ACR non debug",
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gcplex_config);
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} else {
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nvgpu_err(g, "gcplex_config = 0x%08x "
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"invalid wpr_enabled/vpr_auto_fetch_disable "
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"with priv_sec_en", gcplex_config);
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/* do not try to boot GPU */
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return -EINVAL;
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}
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} else {
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__nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false);
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__nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false);
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nvgpu_log(g, gpu_dbg_info,
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"gcplex_config = 0x%08x, non secure mode",
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gcplex_config);
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}
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return 0;
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}
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bool gp10b_fuse_is_opt_ecc_enable(struct gk20a *g)
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{
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return gk20a_readl(g, fuse_opt_ecc_en_r()) != 0U;
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}
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bool gp10b_fuse_is_opt_feature_override_disable(struct gk20a *g)
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{
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return gk20a_readl(g,
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fuse_opt_feature_fuses_override_disable_r()) != 0U;
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}
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