Seshendra Gadagottu b811a0b755 gpu: nvgpu: add hal for fecs ctsw clear mailbox ...

Add hal to have chip specific fecs ctxsw mailbox clear function.
This hal has following prototype with mailbox reg_index and bitmask
for clear_val:
void (*fecs_ctxsw_clear_mailbox)(struct gk20a *g,
			u32 reg_index, u32  clear_val);

JIRA NVGPU-4870

Change-Id: I1d20309224f856872dc97040ecf7628c60fb2802
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2287921
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2020-12-15 14:13:28 -06:00

..

nvgpu

gpu: nvgpu: add hal for fecs ctsw clear mailbox

2020-12-15 14:13:28 -06:00

Makefile

nvgpu: use kernel overlay features

2017-10-29 11:00:55 -07:00