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git://nv-tegra.nvidia.com/linux-nvgpu.git
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b82f2075ae
Created gr falcon hal unit with moving following hal functions from gr to gr falcon: u32 (*fecs_base_addr)(void); u32 (*gpccs_base_addr)(void); void (*dump_stats)(struct gk20a *g); u32 (*fecs_ctxsw_mailbox_size)(void); u32 (*get_fecs_ctx_state_store_major_rev_id)(struct gk20a *g); Modified chip hals to populate these new functions and related code now refers to gr falcon hals. Modified kernel headers to have following defs for fecs/gpccs base address in gm20b/gp10b/gv11b/tu104: static inline u32 gr_fecs_irqsset_r(void); static inline u32 gr_gpcs_gpccs_irqsset_r(void); Created base gm20b hals for fecs/gpccs_base_addr and removed redundant gp106 related hals. JIRA NVGPU-1881 Change-Id: I16e820cc1c89223f57988f1e5723fd8fdcbfe89d Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2081245 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
57 lines
2.0 KiB
C
57 lines
2.0 KiB
C
/*
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* Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/pmu.h>
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#include <nvgpu/log.h>
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#include <nvgpu/timers.h>
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#include <nvgpu/kmem.h>
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#include <nvgpu/dma.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/pmuif/nvgpu_gpmu_cmdif.h>
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void nvgpu_pmu_dump_elpg_stats(struct nvgpu_pmu *pmu)
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{
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struct gk20a *g = pmu->g;
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/* Print PG stats */
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nvgpu_err(g, "Print PG stats");
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nvgpu_falcon_print_dmem(&pmu->flcn,
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pmu->pmu_pg.stat_dmem_offset[PMU_PG_ELPG_ENGINE_ID_GRAPHICS],
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(u32)sizeof(struct pmu_pg_stats_v2));
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g->ops.pmu.pmu_dump_elpg_stats(pmu);
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}
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void nvgpu_pmu_dump_falcon_stats(struct nvgpu_pmu *pmu)
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{
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struct gk20a *g = pmu->g;
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nvgpu_falcon_dump_stats(&pmu->flcn);
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g->ops.pmu.pmu_dump_falcon_stats(pmu);
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nvgpu_err(g, "pmu state: %d", pmu->pmu_state);
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nvgpu_err(g, "elpg state: %d", pmu->pmu_pg.elpg_stat);
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/* PMU may crash due to FECS crash. Dump FECS status */
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g->ops.gr.falcon.dump_stats(g);
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}
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