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The Tegra SOC nvlink driver and dGPU nvlink driver depend on struct definitions, macros and functions exposed by nvlink-core driver. The nvlink-core driver is not part of the nvgpu driver, hence we should not be directly accessing any core driver APIs/macros/structs from the /common/nvlink code. Common code can only use nvgpu internal APIs. We wrap all calls from common/nvlink.c to other drivers in nvgpu wrappers, and define the implementation of wrappers in os/linux and os/nvgpu_rmos, and stub them in os/posix. Also, we remove the implicit inclusion of OS specific nvlink header file via common nvgpu/nvlink.h. So the OS specific code needs to explicitly add OS specific header file. JIRA NVGPU-966 Change-Id: I65c67e247ee74088bb1253f6ae4c8d0c49420a98 Signed-off-by: Tejal Kudav <tkudav@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1990071 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Antony Clince Alex <aalex@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
288 lines
6.2 KiB
C
288 lines
6.2 KiB
C
/*
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* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/gk20a.h>
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#include <nvgpu/nvlink.h>
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#include <nvgpu/enabled.h>
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#include <nvgpu/firmware.h>
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#ifdef CONFIG_TEGRA_NVLINK
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/*
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* WAR: use this function to find detault link, as only one is supported
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* on the library for now
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* Returns NVLINK_MAX_LINKS_SW on failure
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*/
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static u32 nvgpu_nvlink_get_link(struct gk20a *g)
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{
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u32 link_id;
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if (!g)
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return NVLINK_MAX_LINKS_SW;
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/* Lets find the detected link */
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if (g->nvlink.initialized_links)
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link_id = ffs(g->nvlink.initialized_links) - 1;
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else
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return NVLINK_MAX_LINKS_SW;
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if (g->nvlink.links[link_id].remote_info.is_connected)
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return link_id;
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return NVLINK_MAX_LINKS_SW;
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}
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int nvgpu_nvlink_speed_config(struct gk20a *g)
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{
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return g->ops.nvlink.speed_config(g);
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}
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int nvgpu_nvlink_early_init(struct gk20a *g)
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{
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return g->ops.nvlink.early_init(g);
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}
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int nvgpu_nvlink_link_early_init(struct gk20a *g)
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{
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u32 link_id;
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/*
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* First check the topology and setup connectivity
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* HACK: we are only enabling one link for now!!!
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*/
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link_id = ffs(g->nvlink.discovered_links) - 1;
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g->nvlink.links[link_id].remote_info.is_connected = true;
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g->nvlink.links[link_id].remote_info.device_type =
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nvgpu_nvlink_endp_tegra;
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return g->ops.nvlink.link_early_init(g, BIT(link_id));
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}
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int nvgpu_nvlink_interface_init(struct gk20a *g)
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{
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int err;
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err = g->ops.nvlink.interface_init(g);
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return err;
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}
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int nvgpu_nvlink_interface_disable(struct gk20a *g)
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{
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int err = 0;
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if (g->ops.nvlink.interface_disable)
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err = g->ops.nvlink.interface_disable(g);
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return err;
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}
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int nvgpu_nvlink_dev_shutdown(struct gk20a *g)
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{
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int err;
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err = g->ops.nvlink.shutdown(g);
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return 0;
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}
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int nvgpu_nvlink_reg_init(struct gk20a *g)
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{
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int err;
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err = g->ops.nvlink.reg_init(g);
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return err;
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}
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u32 nvgpu_nvlink_get_link_mode(struct gk20a *g)
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{
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u32 link_id;
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link_id = nvgpu_nvlink_get_link(g);
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if (link_id == NVLINK_MAX_LINKS_SW)
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return -EINVAL;
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return g->ops.nvlink.link_get_mode(g, link_id);
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}
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u32 nvgpu_nvlink_get_link_state(struct gk20a *g)
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{
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u32 link_id;
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link_id = nvgpu_nvlink_get_link(g);
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if (link_id == NVLINK_MAX_LINKS_SW)
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return -EINVAL;
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return g->ops.nvlink.link_get_state(g, link_id);
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}
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int nvgpu_nvlink_set_link_mode(struct gk20a *g, u32 mode)
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{
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u32 link_id;
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link_id = nvgpu_nvlink_get_link(g);
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if (link_id == NVLINK_MAX_LINKS_SW)
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return -EINVAL;
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return g->ops.nvlink.link_set_mode(g, link_id, mode);
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}
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void nvgpu_nvlink_get_tx_sublink_state(struct gk20a *g, u32 *state)
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{
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u32 link_id;
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link_id = nvgpu_nvlink_get_link(g);
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if (link_id == NVLINK_MAX_LINKS_SW)
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return;
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if (state)
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*state = g->ops.nvlink.get_tx_sublink_state(g, link_id);
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}
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void nvgpu_nvlink_get_rx_sublink_state(struct gk20a *g, u32 *state)
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{
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u32 link_id;
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link_id = nvgpu_nvlink_get_link(g);
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if (link_id == NVLINK_MAX_LINKS_SW)
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return;
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if (state)
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*state = g->ops.nvlink.get_rx_sublink_state(g, link_id);
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}
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u32 nvgpu_nvlink_get_sublink_mode(struct gk20a *g, bool is_rx_sublink)
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{
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u32 link_id;
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link_id = nvgpu_nvlink_get_link(g);
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if (link_id == NVLINK_MAX_LINKS_SW)
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return -EINVAL;
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return g->ops.nvlink.get_sublink_mode(g, link_id, is_rx_sublink);
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}
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int nvgpu_nvlink_set_sublink_mode(struct gk20a *g,
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bool is_rx_sublink, u32 mode)
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{
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u32 link_id;
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link_id = nvgpu_nvlink_get_link(g);
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if (link_id == NVLINK_MAX_LINKS_SW)
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return -EINVAL;
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return g->ops.nvlink.set_sublink_mode(g, link_id, is_rx_sublink, mode);
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}
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/* Extract a WORD from the MINION ucode */
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u32 nvgpu_nvlink_minion_extract_word(struct nvgpu_firmware *fw, u32 idx)
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{
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u32 out_data = 0;
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u8 byte = 0;
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u32 i = 0;
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for (i = 0; i < 4; i++) {
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byte = fw->data[idx + i];
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out_data |= ((u32)byte) << (8 * i);
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}
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return out_data;
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}
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#endif
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int nvgpu_nvlink_probe(struct gk20a *g)
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{
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#ifdef CONFIG_TEGRA_NVLINK
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int err;
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err = nvgpu_nvlink_setup_ndev(g);
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if (err != 0)
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return err;
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err = nvgpu_nvlink_read_dt_props(g);
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if (err != 0)
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goto free_ndev;
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err = nvgpu_nvlink_init_ops(g);
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if (err != 0)
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goto free_ndev;
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/* Register device with core driver*/
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err = nvgpu_nvlink_register_device(g);
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if (err != 0) {
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nvgpu_err(g, "failed on nvlink device registration");
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goto free_ndev;
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}
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/* Register link with core driver */
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err = nvgpu_nvlink_register_link(g);
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if (err != 0) {
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nvgpu_err(g, "failed on nvlink link registration");
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goto unregister_ndev;
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}
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/* Enable NVLINK support */
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nvgpu_set_enabled(g, NVGPU_SUPPORT_NVLINK, true);
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return 0;
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unregister_ndev:
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nvgpu_nvlink_unregister_device(g);
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free_ndev:
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nvgpu_kfree(g, g->nvlink.priv);
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g->nvlink.priv = NULL;
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return err;
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#else
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return -ENODEV;
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#endif
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}
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int nvgpu_nvlink_remove(struct gk20a *g)
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{
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#ifdef CONFIG_TEGRA_NVLINK
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int err;
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if (!nvgpu_is_enabled(g, NVGPU_SUPPORT_NVLINK))
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return -ENODEV;
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nvgpu_set_enabled(g, NVGPU_SUPPORT_NVLINK, false);
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err = nvgpu_nvlink_unregister_link(g);
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if (err != 0) {
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nvgpu_err(g, "failed on nvlink link unregistration");
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return err;
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}
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err = nvgpu_nvlink_unregister_device(g);
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if (err != 0) {
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nvgpu_err(g, "failed on nvlink device unregistration");
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return err;
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}
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nvgpu_kfree(g, g->nvlink.priv);
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return 0;
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#else
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return -ENODEV;
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#endif
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}
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