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RPC handlers for therm, volt, perfmon and acr were open coded in the pmu_rpc_handler. Instead, add implementations to respective units. To avoid the dereferncing of struct nvgpu_pmu to avoid the circular dependency we pass gk20a struct as input to nvgpu_pmu_rpc_execute and other pmu_ipc.c functions. JIRA NVGPU-1970 Change-Id: I6ea046960936923e69242bf90e8e25958cfba85e Signed-off-by: Sagar Kamble <skamble@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2079145 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-by: Ankur Kishore <ankkishore@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
158 lines
3.7 KiB
C
158 lines
3.7 KiB
C
/*
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* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/types.h>
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#include <nvgpu/dma.h>
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#include <nvgpu/firmware.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/pmuif/gpmuif_cmn.h>
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#include "acr_priv.h"
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#include "acr_sw_gm20b.h"
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#include "acr_sw_gp10b.h"
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#include "acr_sw_gv100.h"
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#include "acr_sw_gv11b.h"
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#include "acr_sw_tu104.h"
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/* ACR public API's */
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bool nvgpu_acr_is_lsf_lazy_bootstrap(struct gk20a *g, struct nvgpu_acr *acr,
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u32 falcon_id)
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{
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if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL) || acr == NULL) {
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return false;
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}
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return acr->lsf[falcon_id].is_lazy_bootstrap;
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}
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int nvgpu_acr_alloc_blob_prerequisite(struct gk20a *g, struct nvgpu_acr *acr,
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size_t size)
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{
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if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) {
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return 0;
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}
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if (acr == NULL) {
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return -EINVAL;
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}
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return acr->alloc_blob_space(g, size, &acr->ucode_blob);
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}
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/* ACR blob construct & bootstrap */
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int nvgpu_acr_bootstrap_hs_acr(struct gk20a *g, struct nvgpu_acr *acr)
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{
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int err = 0;
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if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) {
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return 0;
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}
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if (acr == NULL) {
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return -EINVAL;
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}
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err = acr->bootstrap_hs_acr(g, acr, &acr->acr);
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if (err != 0) {
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nvgpu_err(g, "ACR bootstrap failed");
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}
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return err;
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}
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int nvgpu_acr_construct_execute(struct gk20a *g, struct nvgpu_acr *acr)
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{
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int err = 0;
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if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) {
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return 0;
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}
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if (acr == NULL) {
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return -EINVAL;
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}
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err = acr->prepare_ucode_blob(g);
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if (err != 0) {
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nvgpu_err(g, "ACR ucode blob prepare failed");
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goto done;
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}
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err = nvgpu_acr_bootstrap_hs_acr(g, acr);
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done:
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return err;
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}
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/* ACR init */
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int nvgpu_acr_init(struct gk20a *g, struct nvgpu_acr **acr)
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{
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u32 ver = g->params.gpu_arch + g->params.gpu_impl;
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int err = 0;
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if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) {
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goto done;
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}
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if (*acr != NULL) {
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/*
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* Recovery/unrailgate case, we do not need to do ACR init as ACR is
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* set during cold boot & doesn't execute ACR clean up as part off
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* sequence, so reuse to perform faster boot.
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*/
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return err;
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}
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*acr = (struct nvgpu_acr *) nvgpu_kzalloc(g, sizeof(struct nvgpu_acr));
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if (g->acr == NULL) {
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err = -ENOMEM;
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goto done;
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}
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switch (ver) {
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case GK20A_GPUID_GM20B:
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case GK20A_GPUID_GM20B_B:
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nvgpu_gm20b_acr_sw_init(g, *acr);
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break;
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case NVGPU_GPUID_GP10B:
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nvgpu_gp10b_acr_sw_init(g, *acr);
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break;
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case NVGPU_GPUID_GV11B:
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nvgpu_gv11b_acr_sw_init(g, *acr);
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break;
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case NVGPU_GPUID_GV100:
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nvgpu_gv100_acr_sw_init(g, *acr);
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break;
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case NVGPU_GPUID_TU104:
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nvgpu_tu104_acr_sw_init(g, *acr);
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break;
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default:
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nvgpu_kfree(g, *acr);
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err = -EINVAL;
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nvgpu_err(g, "no support for GPUID %x", ver);
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break;
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}
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done:
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return err;
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}
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