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git://nv-tegra.nvidia.com/linux-nvgpu.git
synced 2025-12-22 17:36:20 +03:00
869735cda4
Add gv11b and tu104 HALs to get allowed HWPM resource register ranges, offsets, and stride meta data. Add new enum nvgpu_pm_resource_hwpm_register_type for HWPM register type. Add new struct nvgpu_pm_resource_register_range_map to store all the register ranges for HWPM resources. Add pointer of map in struct nvgpu_profiler_object along with map entry count. Add new API nvgpu_profiler_build_regops_allowlist() to build the regops allowlist dynamically while binding the resources. Map entry count is received with get_pm_resource_register_range_map_entry_count() and only those resource ranges are added for which resource is reserved by profiler object. Add nvgpu_profiler_destroy_regops_allowlist() to destroy the allowlist while unbinding the resources. Add static functions allowlist_range_search() to search a register offset in HWPM resource ranges. Add another static function allowlist_offset_search() to search the offset in per-resource offset list. Add nvgpu_profiler_validate_regops_allowlist() that accepts an offset value, checks if it is in allowed ranges using allowlist_range_search() and then checks if offset is in allowlist using allowlist_offset_search(). Update gops.regops.exec_regops() to receive profiler object pointer as a parameter. Invoke nvgpu_profiler_validate_regops_allowlist() from validate_reg_ops() if prof pointer is not-null. This will be true only for new profiler stack and not legacy profilers. In gr_exec_ctx_ops(), skip regops execution if offset is invalid. Bug 2510974 Jira NVGPU-5360 Change-Id: I40acb91cc37508629c83106ea15b062250bba473 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2460001 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> Reviewed-by: Antony Clince Alex <aalex@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit
119 lines
3.4 KiB
C
119 lines
3.4 KiB
C
/*
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* Copyright (c) 2015-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/vgpu/vgpu_ivc.h>
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#include <nvgpu/vgpu/tegra_vgpu.h>
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#include <nvgpu/vgpu/vgpu.h>
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#include <nvgpu/debugger.h>
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#include <nvgpu/profiler.h>
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#include <nvgpu/bug.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/channel.h>
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#include <nvgpu/string.h>
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#include <nvgpu/regops.h>
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#include "debugger_vgpu.h"
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#include "common/vgpu/ivc/comm_vgpu.h"
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int vgpu_exec_regops(struct gk20a *g,
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struct nvgpu_tsg *tsg,
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struct nvgpu_profiler_object *prof,
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struct nvgpu_dbg_reg_op *ops,
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u32 num_ops,
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u32 *flags)
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{
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struct tegra_vgpu_cmd_msg msg;
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struct tegra_vgpu_reg_ops_params *p = &msg.params.reg_ops;
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void *oob;
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size_t oob_size, ops_size;
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void *handle = NULL;
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int err = 0;
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nvgpu_log_fn(g, " ");
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BUG_ON(sizeof(*ops) != sizeof(struct tegra_vgpu_reg_op));
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handle = vgpu_ivc_oob_get_ptr(vgpu_ivc_get_server_vmid(),
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TEGRA_VGPU_QUEUE_CMD,
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&oob, &oob_size);
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if (!handle) {
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return -EINVAL;
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}
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ops_size = sizeof(*ops) * num_ops;
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if (oob_size < ops_size) {
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err = -ENOMEM;
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goto fail;
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}
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nvgpu_memcpy((u8 *)oob, (u8 *)ops, ops_size);
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msg.cmd = TEGRA_VGPU_CMD_REG_OPS;
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msg.handle = vgpu_get_handle(g);
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p->tsg_id = tsg ? tsg->tsgid : U32_MAX;
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p->num_ops = num_ops;
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p->flags = *flags;
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err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
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err = err ? err : msg.ret;
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if (err == 0) {
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nvgpu_memcpy((u8 *)ops, (u8 *)oob, ops_size);
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}
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*flags = p->flags;
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fail:
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vgpu_ivc_oob_put_ptr(handle);
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return err;
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}
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int vgpu_dbg_set_powergate(struct dbg_session_gk20a *dbg_s,
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bool disable_powergate)
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{
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struct tegra_vgpu_cmd_msg msg;
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struct tegra_vgpu_set_powergate_params *p = &msg.params.set_powergate;
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int err = 0;
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u32 mode;
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struct gk20a *g = dbg_s->g;
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nvgpu_log_fn(g, " ");
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/* Just return if requested mode is the same as the session's mode */
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if (disable_powergate) {
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if (dbg_s->is_pg_disabled) {
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return 0;
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}
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dbg_s->is_pg_disabled = true;
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mode = TEGRA_VGPU_POWERGATE_MODE_DISABLE;
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} else {
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if (!dbg_s->is_pg_disabled) {
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return 0;
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}
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dbg_s->is_pg_disabled = false;
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mode = TEGRA_VGPU_POWERGATE_MODE_ENABLE;
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}
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msg.cmd = TEGRA_VGPU_CMD_SET_POWERGATE;
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msg.handle = vgpu_get_handle(dbg_s->g);
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p->mode = mode;
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err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
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err = err ? err : msg.ret;
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return err;
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}
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