Philip Elcan a3ba265dd6 gpu: nvgpu: mm: fix MISRA 10.3 violations ...

MISRA Rule 10.3 prohibits implicit assignment of objects of different
size or essential type. This resolves a number of 10.3 violations in the
nvgpu/common/mm unit.

JIRA NVGPU-2935

Change-Id: Ic9d826bf67417962aab433d08d3e922de26e3edc
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2036117
GVS: Gerrit_Virtual_Submit
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

2019-03-12 08:56:33 -07:00

..

page_table.c

gpu: nvgpu: mm: fix MISRA 10.3 violations

2019-03-12 08:56:33 -07:00

pd_cache_priv.h

gpu: nvgpu: create pd_cache_priv.h

2019-03-05 11:14:50 -08:00

pd_cache.c

gpu: nvgpu: create pd_cache_priv.h

2019-03-05 11:14:50 -08:00