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7f6c782ba0
MISRA Rule 10.4 only allows the usage of arithmetic operations on operands of the same essential type category. Adding "U" at the end of the integer literals to have same type of operands when an arithmetic operation is performed. This fixes violation where an arithmetic operation is performed on signed and unsigned int types. JIRA NVGPU-992 Change-Id: Ic8e5ae1ab71c6ecdfed83deeb4f354a1d1dbe8ed Signed-off-by: Sai Nikhil <snikhil@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1810614 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Scott Long <scottl@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
113 lines
4.5 KiB
C
113 lines
4.5 KiB
C
/*
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* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_CTRLCLKAVFS_H
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#define NVGPU_CTRLCLKAVFS_H
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#include "ctrlboardobj.h"
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/*!
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* Valid global VIN ID values
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*/
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#define CTRL_CLK_VIN_ID_SYS 0x00000000U
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#define CTRL_CLK_VIN_ID_LTC 0x00000001U
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#define CTRL_CLK_VIN_ID_XBAR 0x00000002U
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#define CTRL_CLK_VIN_ID_GPC0 0x00000003U
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#define CTRL_CLK_VIN_ID_GPC1 0x00000004U
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#define CTRL_CLK_VIN_ID_GPC2 0x00000005U
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#define CTRL_CLK_VIN_ID_GPC3 0x00000006U
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#define CTRL_CLK_VIN_ID_GPC4 0x00000007U
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#define CTRL_CLK_VIN_ID_GPC5 0x00000008U
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#define CTRL_CLK_VIN_ID_GPCS 0x00000009U
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#define CTRL_CLK_VIN_ID_SRAM 0x0000000AU
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#define CTRL_CLK_VIN_ID_UNDEFINED 0x000000FFU
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#define CTRL_CLK_VIN_TYPE_DISABLED 0x00000000U
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#define CTRL_CLK_VIN_TYPE_V10 0x00000001U
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#define CTRL_CLK_VIN_TYPE_V20 0x00000002U
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/*!
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* Various types of VIN calibration that the GPU can support
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*/
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#define CTRL_CLK_VIN_CAL_TYPE_V10 (0x00000000U)
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#define CTRL_CLK_VIN_CAL_TYPE_V20 (0x00000001U)
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/*!
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* Mask of all GPC VIN IDs supported by RM
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*/
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#define CTRL_CLK_VIN_MASK_UNICAST_GPC (BIT(CTRL_CLK_VIN_ID_GPC0) | \
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BIT(CTRL_CLK_VIN_ID_GPC1) | \
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BIT(CTRL_CLK_VIN_ID_GPC2) | \
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BIT(CTRL_CLK_VIN_ID_GPC3) | \
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BIT(CTRL_CLK_VIN_ID_GPC4) | \
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BIT(CTRL_CLK_VIN_ID_GPC5))
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#define CTRL_CLK_LUT_NUM_ENTRIES_MAX (128U)
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#define CTRL_CLK_LUT_NUM_ENTRIES_GV10x (128U)
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#define CTRL_CLK_LUT_NUM_ENTRIES_GP10x (100U)
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#define CTRL_CLK_VIN_STEP_SIZE_UV (10000U)
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#define CTRL_CLK_LUT_MIN_VOLTAGE_UV (450000U)
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#define CTRL_CLK_FLL_TYPE_DISABLED 0U
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#define CTRL_CLK_FLL_ID_SYS (0x00000000U)
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#define CTRL_CLK_FLL_ID_LTC (0x00000001U)
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#define CTRL_CLK_FLL_ID_XBAR (0x00000002U)
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#define CTRL_CLK_FLL_ID_GPC0 (0x00000003U)
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#define CTRL_CLK_FLL_ID_GPC1 (0x00000004U)
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#define CTRL_CLK_FLL_ID_GPC2 (0x00000005U)
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#define CTRL_CLK_FLL_ID_GPC3 (0x00000006U)
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#define CTRL_CLK_FLL_ID_GPC4 (0x00000007U)
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#define CTRL_CLK_FLL_ID_GPC5 (0x00000008U)
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#define CTRL_CLK_FLL_ID_GPCS (0x00000009U)
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#define CTRL_CLK_FLL_ID_UNDEFINED (0x000000FFU)
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#define CTRL_CLK_FLL_MASK_UNDEFINED (0x00000000U)
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/*!
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* Mask of all GPC FLL IDs supported by RM
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*/
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#define CTRL_CLK_FLL_MASK_UNICAST_GPC (BIT(CTRL_CLK_FLL_ID_GPC0) | \
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BIT(CTRL_CLK_FLL_ID_GPC1) | \
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BIT(CTRL_CLK_FLL_ID_GPC2) | \
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BIT(CTRL_CLK_FLL_ID_GPC3) | \
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BIT(CTRL_CLK_FLL_ID_GPC4) | \
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BIT(CTRL_CLK_FLL_ID_GPC5))
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/*!
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* Mask of all FLL IDs supported by Nvgpu driver
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*/
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#define CTRL_CLK_FLL_ID_ALL_MASK (BIT(CTRL_CLK_FLL_ID_SYS) | \
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BIT(CTRL_CLK_FLL_ID_LTC) | \
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BIT(CTRL_CLK_FLL_ID_XBAR) | \
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BIT(CTRL_CLK_FLL_ID_GPC0) | \
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BIT(CTRL_CLK_FLL_ID_GPC1) | \
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BIT(CTRL_CLK_FLL_ID_GPC2) | \
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BIT(CTRL_CLK_FLL_ID_GPC3) | \
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BIT(CTRL_CLK_FLL_ID_GPC4) | \
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BIT(CTRL_CLK_FLL_ID_GPC5) | \
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BIT(CTRL_CLK_FLL_ID_GPCS))
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#define CTRL_CLK_FLL_REGIME_ID_INVALID (0x00000000U)
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#define CTRL_CLK_FLL_REGIME_ID_FFR (0x00000001U)
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#define CTRL_CLK_FLL_REGIME_ID_FR (0x00000002U)
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#define CTRL_CLK_FLL_LUT_VSELECT_LOGIC (0x00000000U)
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#define CTRL_CLK_FLL_LUT_VSELECT_MIN (0x00000001U)
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#define CTRL_CLK_FLL_LUT_VSELECT_SRAM (0x00000002U)
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#endif /* NVGPU_CTRLCLKAVFS_H */
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