mirror of
git://nv-tegra.nvidia.com/linux-nvgpu.git
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bcbccbe083
Update nvgpu_rc_mmu_fault to return error on invalid params and add BVEC test for it. JIRA NVGPU-6772 Change-Id: If44d80888c665ca3b528c9937de8a66ccce29f57 Signed-off-by: Sagar Kamble <skamble@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2551618 (cherry picked from commit 229727512a1facc33ef9f16cc1831405e960ab2a) Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2623626 Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com> GVS: Gerrit_Virtual_Submit
337 lines
9.9 KiB
C
337 lines
9.9 KiB
C
/*
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* Copyright (c) 2019-2022, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef UNIT_NVGPU_RC_H
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#define UNIT_NVGPU_RC_H
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#include <nvgpu/types.h>
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struct gk20a;
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struct unit_module;
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/** @addtogroup SWUTS-nvgpu-rc
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* @{
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*
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* Software Unit Test Specification for nvgpu-rc
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*/
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/**
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* Test specification for: test_rc_init
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*
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* Description: Environment initialization for rc tests
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*
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* Test Type: Other (setup)
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*
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* Input: None
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*
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* Steps:
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* - init FIFO register space.
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* - init HAL parameters for gv11b.
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* - init fifo support for Channel and TSG
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* - init Runlist setup
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* - open a TSG
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* - open a new Channel
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* - allocate memory for posix_channel
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* - bind Channel to TSG
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*
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* Output: Returns PASS if all the above steps are successful. FAIL otherwise.
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*/
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int test_rc_init(struct unit_module *m, struct gk20a *g, void *args);
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/**
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* Test specification for: test_rc_deinit
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*
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* Description: Environment de-initialization for rc tests
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*
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* Test Type: Other (cleanup)
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*
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* Input: test_rc_init run for this GPU
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*
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* Steps:
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* - unbind Channel from TSG
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* - free posix_channel
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* - close Channel
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* - close TSG
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* - remove FIFO support
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* - clear FIFO register space
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*
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* Output: Returns PASS if all the above steps are successful. FAIL otherwise.
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*/
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int test_rc_deinit(struct unit_module *m, struct gk20a *g, void *args);
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/**
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* Test specification for: test_rc_fifo_recover
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*
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* Description: Coverage test for nvgpu_rc_fifo_recover
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*
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* Test Type: Feature
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*
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* Targets: nvgpu_rc_fifo_recover
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*
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* Input: test_rc_init run for this GPU
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*
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* Steps:
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* - initialize Channel error_notifier
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* - set g->sw_quiesce_pending = true
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* - invoke nvgpu_rc_fifo_recover
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*
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* Output: Cover all branch in safety build.
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*/
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int test_rc_fifo_recover(struct unit_module *m, struct gk20a *g, void *args);
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/**
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* Test specification for: test_rc_ctxsw_timeout
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*
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* Description: Coverage test for nvgpu_rc_ctxsw_timeout
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*
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* Test Type: Feature
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*
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* Targets: nvgpu_rc_ctxsw_timeout
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*
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* Input: test_rc_init run for this GPU
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*
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* Steps:
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* - initialize Channel error_notifier
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* - set g->sw_quiesce_pending = true
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* - invoke nvgpu_rc_ctxsw_timeout
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* - verfy that error_notifier is set to NVGPU_ERR_NOTIFIER_FIFO_ERROR_IDLE_TIMEOUT
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*
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* Output: Cover all branch in safety build.
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*/
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int test_rc_ctxsw_timeout(struct unit_module *m, struct gk20a *g, void *args);
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/**
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* Test specification for: test_rc_runlist_update
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*
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* Description: Coverage test for nvgpu_rc_runlist_update
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*
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* Test Type: Feature
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*
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* Targets: nvgpu_rc_runlist_update
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*
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* Input: test_rc_init run for this GPU
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*
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* Steps:
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* - initialize Channel error_notifier
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* - set g->sw_quiesce_pending = true
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* - invoke nvgpu_rc_runlist_update
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*
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* Output: Cover all branch in safety build.
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*/
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int test_rc_runlist_update(struct unit_module *m, struct gk20a *g, void *args);
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/**
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* Test specification for: test_rc_preempt_timeout
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*
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* Description: Coverage test for nvgpu_rc_preempt_timeout
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*
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* Test Type: Feature
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*
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* Targets: nvgpu_rc_preempt_timeout
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*
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* Input: test_rc_init run for this GPU
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*
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* Steps:
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* - initialize Channel error_notifier
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* - set g->sw_quiesce_pending = true
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* - invoke nvgpu_rc_preempt_timeout
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* - verfy that error_notifier is set to NVGPU_ERR_NOTIFIER_FIFO_ERROR_IDLE_TIMEOUT
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*
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* Output: Cover all branch in safety build.
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*/
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int test_rc_preempt_timeout(struct unit_module *m, struct gk20a *g, void *args);
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/**
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* Test specification for: test_rc_gr_fault
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*
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* Description: Coverage test for nvgpu_rc_gr_fault
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*
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* Test Type: Feature
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*
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* Targets: nvgpu_rc_gr_fault
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*
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* Input: test_rc_init run for this GPU
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*
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* Steps:
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* - initialize Channel error_notifier
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* - set g->sw_quiesce_pending = true
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* - invoke nvgpu_rc_gr_fault
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*
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* Output: Cover all branch in safety build.
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*/
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int test_rc_gr_fault(struct unit_module *m, struct gk20a *g, void *args);
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/**
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* Test specification for: test_rc_sched_error_bad_tsg
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*
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* Description: Coverage test for nvgpu_rc_sched_error_bad_tsg
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*
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* Test Type: Feature
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*
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* Targets: nvgpu_rc_sched_error_bad_tsg
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*
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* Input: test_rc_init run for this GPU
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*
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* Steps:
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* - initialize Channel error_notifier
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* - set g->sw_quiesce_pending = true
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* - invoke nvgpu_rc_sched_error_bad_tsg
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*
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* Output: Cover all branch in safety build.
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*/
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int test_rc_sched_error_bad_tsg(struct unit_module *m, struct gk20a *g, void *args);
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/**
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* Test specification for: test_rc_tsg_and_related_engines
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*
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* Description: Coverage test for nvgpu_rc_tsg_and_related_engines
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*
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* Test Type: Feature
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*
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* Targets: nvgpu_rc_tsg_and_related_engines
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*
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* Input: test_rc_init run for this GPU
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*
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* Steps:
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* - initialize Channel error_notifier
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* - set g->sw_quiesce_pending = true
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* - invoke nvgpu_rc_tsg_and_related_engines
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*
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* Output: Cover all branch in safety build.
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*/
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int test_rc_tsg_and_related_engines(struct unit_module *m, struct gk20a *g, void *args);
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/**
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* Test specification for: test_rc_mmu_fault
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*
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* Description: Coverage test for nvgpu_rc_mmu_fault
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*
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* Test Type: Feature
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*
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* Targets: nvgpu_rc_mmu_fault
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*
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* Input: test_rc_init run for this GPU
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*
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* Steps:
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* - initialize Channel error_notifier
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* - set g->sw_quiesce_pending = true
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* - set invalid_id
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* - invoke nvgpu_rc_mmu_fault
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* - set id_type_tsg
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* - invoke nvgpu_rc_mmu_fault
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* - set id_type_non_tsg
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* - invoke nvgpu_rc_mmu_fault
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*
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* Output: Cover all branch in safety build.
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*/
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int test_rc_mmu_fault(struct unit_module *m, struct gk20a *g, void *args);
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/**
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* Test specification for: test_rc_mmu_fault_bvec
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*
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* Description: Validate id and id_type parameters for nvgpu_rc_mmu_fault
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*
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* Test Type: Boundary Value
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*
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* Targets: nvgpu_rc_mmu_fault
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*
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* Input: test_rc_init run for this GPU
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*
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* Equivalence classes:
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* Variable: id
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* - Valid: [0, g->fifo.num_channels - 1]
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* - Invalid: [g->fifo.num_channels, INVAL_ID]
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* Variable: id_type
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* - Valid: [ID_TYPE_CHANNEL, ID_TYPE_TSG]
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* - Invalid: [ID_TYPE_TSG + 1, ID_TYPE_UNKNOWN]
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*
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* Steps:
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* - initialize Channel error_notifier
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* - set g->sw_quiesce_pending = true
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* - for all valid ids with ID_TYPE_TSG
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* - invoke nvgpu_rc_mmu_fault and verify it succeeds with return value 0.
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* - for all invalid ids with ID_TYPE_TSG
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* - invoke nvgpu_rc_mmu_fault and verify it fails with -EINVAL.
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* - for all valid id types with id ID_TYPE_CHANNEL
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* - invoke nvgpu_rc_mmu_fault and verify it succeeds with return value 0.
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* - for all invalid id types with id ID_TYPE_CHANNEL
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* - invoke nvgpu_rc_mmu_fault and verify it fails with -EINVAL.
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*
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* Output: Returns PASS if nvgpu_rc_mmu_fault succeeds for valid id and id_type
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* and fails for invalid id and id_type. Returns FAIL otherwise.
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*/
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int test_rc_mmu_fault_bvec(struct unit_module *m, struct gk20a *g, void *args);
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/**
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* Test specification for: test_rc_pbdma_fault
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*
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* Description: Coverage test for nvgpu_rc_pbdma_fault
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*
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* Test Type: Feature, Boundary Value
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*
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* Targets: nvgpu_rc_pbdma_fault
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*
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* Input: test_rc_init run for this GPU
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*
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* Equivalence classes:
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* Variable: error_notifier
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* - Valid: [NVGPU_ERR_NOTIFIER_FIFO_ERROR_IDLE_TIMEOUT, NVGPU_ERR_NOTIFIER_PBDMA_PUSHBUFFER_CRC_MISMATCH]
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* - Invalid: [NVGPU_ERR_NOTIFIER_INVAL, INT_MAX]
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* Variable: chsw state
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* - Valid: [NVGPU_PBDMA_CHSW_STATUS_INVALID, NVGPU_PBDMA_CHSW_STATUS_SWITCH]
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* - Invalid: [NVGPU_PBDMA_CHSW_STATUS_SWITCH + 1, INT_MAX]
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* Variable: id_type
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* - Valid: [PBDMA_STATUS_ID_TYPE_CHID, PBDMA_STATUS_ID_TYPE_TSGID]
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* - Invalid: [PBDMA_STATUS_ID_TYPE_TSGID + 1, PBDMA_STATUS_ID_TYPE_INVALID]
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*
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* Steps:
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* - initialize Channel error_notifier
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* - test with valid and invalid error notifier values types
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* - set g->sw_quiesce_pending = true
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* - For each branch check with the following pbdma_status values
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* - set chsw_status to chsw_valid_or_save
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* - set id_type to TSG
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* - set id_type to Channel
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* - set Channel Id to Invalid
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* - set Channel Id to a channel without TSG
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* - set Channel Id to a channel with a valid TSG
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* - set id_type to chid, tsgid, tsgid + 1, tsgid + 1 + random, invalid_id
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* - verify that nvgpu_rc_pbdma_fault fails for invalid id_types and invalid channel ids and succeeds otherwise.
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* - set chsw_status to is_chsw_load_or_switch
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* - set id_type to TSG
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* - set id_type to Channel
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* - set Channel Id to Invalid
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* - set Channel Id to a channel without TSG
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* - set Channel Id to a channel with a valid TSG
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* - set id_type to chid, tsgid, tsgid + 1, tsgid + 1 + random, invalid_id
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* - verify that nvgpu_rc_pbdma_fault fails for invalid id_types and invalid channel ids and succeeds otherwise.
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* - set chsw_status to chsw_invalid and verify that nvgpu_rc_pbdma_fault succeeds.
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* - set chsw_status to invalid states and verify that nvgpu_rc_pbdma_fault fails.
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*
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* Output: Returns PASS if nvgpu_rc_pbdma_fault succeeds for valid inputs
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* and fails for invalid inputs. Returns FAIL otherwise.
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*/
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int test_rc_pbdma_fault(struct unit_module *m, struct gk20a *g, void *args);
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/** @} */
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#endif /* UNIT_NVGPU_RC_H */
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