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bcf83fab33
Since all userspace apps are using 64K pages these days it makes sense to set the default large page size to 64K. This in turn causes the PDE coverage field to be set to 64M in the GPU characteristics field. While it would therefor be possible to create a VM with a PDE coverage that's larger than 64M (128M if you set the large page size to 128K) this will make the defaults work properly. This in turn fixes a CUDA issue where CUDA tries to determine the PDE coverage (and correspondingly a minimum alignemnt) from the characteristics IOCTL. Bug 200105199 Change-Id: Iee3c213f1b81d8628571f46c7ad5e16fbfe07499 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1781088 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
89 lines
2.2 KiB
C
89 lines
2.2 KiB
C
/*
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* GM20B MMU
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*
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* Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/sizes.h>
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#include "gk20a/gk20a.h"
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#include "mm_gm20b.h"
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#include <nvgpu/hw/gm20b/hw_gmmu_gm20b.h>
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#include <nvgpu/hw/gm20b/hw_ram_gm20b.h>
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void gm20b_mm_set_big_page_size(struct gk20a *g,
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struct nvgpu_mem *mem, int size)
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{
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u32 val;
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nvgpu_log_fn(g, " ");
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nvgpu_log_info(g, "big page size %d\n", size);
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val = nvgpu_mem_rd32(g, mem, ram_in_big_page_size_w());
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val &= ~ram_in_big_page_size_m();
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if (size == SZ_64K)
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val |= ram_in_big_page_size_64kb_f();
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else
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val |= ram_in_big_page_size_128kb_f();
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nvgpu_mem_wr32(g, mem, ram_in_big_page_size_w(), val);
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nvgpu_log_fn(g, "done");
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}
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u32 gm20b_mm_get_big_page_sizes(void)
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{
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return SZ_64K | SZ_128K;
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}
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u32 gm20b_mm_get_default_big_page_size(void)
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{
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return SZ_64K;
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}
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bool gm20b_mm_support_sparse(struct gk20a *g)
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{
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return true;
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}
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bool gm20b_mm_is_bar1_supported(struct gk20a *g)
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{
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return true;
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}
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u64 gm20b_gpu_phys_addr(struct gk20a *g,
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struct nvgpu_gmmu_attrs *attrs, u64 phys)
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{
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return phys;
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}
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u32 gm20b_get_kind_invalid(void)
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{
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return gmmu_pte_kind_invalid_v();
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}
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u32 gm20b_get_kind_pitch(void)
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{
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return gmmu_pte_kind_pitch_v();
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}
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