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7d3ae08847
Move fifo related code to common/vgpu/fifo and create new child units fifo, channel, tsg, preempt, engines. Also update arch YAML to include newly created files related to fifo unit. Jira GVSCI-994 Change-Id: I79897df4e729e0506702832ba62c1694c3f42280 Signed-off-by: Aparna Das <aparnad@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2138388 Reviewed-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Nirav Patel <nipatel@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
73 lines
2.5 KiB
C
73 lines
2.5 KiB
C
/*
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* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/gk20a.h>
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#include <nvgpu/engines.h>
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#include <nvgpu/fifo.h>
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#include <nvgpu/vgpu/vgpu.h>
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#include "engines_vgpu.h"
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int vgpu_engine_init_info(struct nvgpu_fifo *f)
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{
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struct vgpu_priv_data *priv = vgpu_get_priv_data(f->g);
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struct tegra_vgpu_engines_info *engines = &priv->constants.engines_info;
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u32 i;
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struct gk20a *g = f->g;
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nvgpu_log_fn(g, " ");
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if (engines->num_engines > TEGRA_VGPU_MAX_ENGINES) {
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nvgpu_err(f->g, "num_engines %d larger than max %d",
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engines->num_engines, TEGRA_VGPU_MAX_ENGINES);
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return -EINVAL;
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}
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f->num_engines = engines->num_engines;
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for (i = 0; i < f->num_engines; i++) {
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struct nvgpu_engine_info *info =
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&f->engine_info[engines->info[i].engine_id];
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if (engines->info[i].engine_id >= f->max_engines) {
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nvgpu_err(f->g, "engine id %d larger than max %d",
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engines->info[i].engine_id,
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f->max_engines);
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return -EINVAL;
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}
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info->intr_mask = engines->info[i].intr_mask;
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info->reset_mask = engines->info[i].reset_mask;
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info->runlist_id = engines->info[i].runlist_id;
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info->pbdma_id = engines->info[i].pbdma_id;
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info->inst_id = engines->info[i].inst_id;
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info->pri_base = engines->info[i].pri_base;
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info->engine_enum = engines->info[i].engine_enum;
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info->fault_id = engines->info[i].fault_id;
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f->active_engines_list[i] = engines->info[i].engine_id;
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}
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nvgpu_log_fn(g, "done");
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return 0;
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}
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