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1481fe54e9
This patch removes dependency between pmu.clk and hal.clk. Below is the implementation. *Init the clk domains inside pmu.clk unit. *Set this in a member variable and send it to hal.clk unit *Use this to determine the valid clock domains and read the monitor registers for each valid domains. *Return the domain with error code. *With this all the clk domain data is removed from hal.clk and only pmu.clk uses it as it owns it. JIRA NVGPU-4491 Change-Id: Ie57b2472cfaacfd2ce43ac7f95702bd95fb8bbaa Signed-off-by: Abdul Salam <absalam@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2272416 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
56 lines
2.2 KiB
C
56 lines
2.2 KiB
C
/*
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* Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef CLK_TU104_H
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#define CLK_TU104_H
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#include <nvgpu/lock.h>
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#include <nvgpu/gk20a.h>
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/**
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* FMON register types
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*/
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#define FMON_THRESHOLD_HIGH 0x0U
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#define FMON_THRESHOLD_LOW 0x1U
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#define FMON_FAULT_STATUS 0x2U
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#define FMON_FAULT_STATUS_PRIV_MASK 0x3U
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#define CLK_CLOCK_MON_REG_TYPE_COUNT 0x4U
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#define CLK_MON_BITS_PER_BYTE 0x8U
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u32 tu104_get_rate_cntr(struct gk20a *g, struct namemap_cfg *c);
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int tu104_init_clk_support(struct gk20a *g);
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u32 tu104_crystal_clk_hz(struct gk20a *g);
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unsigned long tu104_clk_measure_freq(struct gk20a *g, u32 api_domain);
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void tu104_suspend_clk_support(struct gk20a *g);
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int tu104_clk_domain_get_f_points(
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struct gk20a *g,
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u32 clkapidomain,
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u32 *pfpointscount,
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u16 *pfreqpointsinmhz);
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unsigned long tu104_clk_maxrate(struct gk20a *g, u32 api_domain);
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void tu104_get_change_seq_time(struct gk20a *g, s64 *change_time);
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void tu104_change_host_clk_source(struct gk20a *g);
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bool nvgpu_clk_mon_check_master_fault_status(struct gk20a *g);
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int nvgpu_clk_mon_check_status(struct gk20a *g, struct
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clk_domains_mon_status_params *clk_mon_status,
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u32 domain_mask);
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#endif /* CLK_TU104_H */
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